core_config.py didn't really work with Python 3 yet

1 files changed, 22 insertions, 26 deletions

diff --git a/config/core_config.py b/config/core_config.py
index d511228..f604522 100755
--- a/config/core_config.py
+++ b/config/core_config.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
 
 """
 Generate core_selector.v and core_vfiles.mk for a set of cores.
@@ -54,12 +54,12 @@ def main():
 
     try:
         cfg = RawConfigParser()
-        cfg.readfp(args.config)
+        cfg.read_file(args.config)
 
         board = args.board or cfg.get("default", "board")
         board_section = "board " + board
         Core.bus_name = cfg.get(board_section, "bus name")
-        Core.bus_width = int(cfg.get(board_section, "bus width"))
+        Core.bus_width = cfg.getint(board_section, "bus width")
         Core.bus_max = Core.bus_width - 1
         Core.addr_width = Core.bus_width - 8
         Core.addr_max = Core.addr_width - 1
@@ -95,7 +95,7 @@ def main():
         core_number = 0
         for core in cores:
             core_number = core.assign_core_number(core_number)
-            
+
         for i, core in enumerate(cores):
             core.assign_seq_number(i)
 
@@ -112,7 +112,7 @@ def main():
             # code entirely results in a non-working bitstream.  Don't
             # know why, disabling the optimization works, so just do
             # that for now.
-            
+
             Core.need_one_cycle_delay = any(core.block_memory for core in cores)
 
         # longest core/subcore instance name
@@ -134,16 +134,13 @@ def main():
         args.makefile.write(listVfiles_template.format(
             vfiles = "".join(core.listVfiles()    for core in cores)))
 
-    except Exception, e:
+    except Exception as e:
         if args.debug:
             raise
         exit(str(e))
 
 
-try:
-    import ConfigParser as configparser
-except ImportError:
-    import configparser   
+import configparser
 
 class RawConfigParser(configparser.RawConfigParser):
     """
@@ -152,8 +149,7 @@ class RawConfigParser(configparser.RawConfigParser):
 
     def getboolean(self, section, option, default = False):
         if self.has_option(section, option):
-            # RawConfigParser is an old-stle class, super() doesn't work, feh.
-            return configparser.RawConfigParser.getboolean(self, section, option)
+            return super().getboolean(section, option)
         else:
             return default
 
@@ -162,9 +158,9 @@ class RawConfigParser(configparser.RawConfigParser):
             for value in self.get(section, option).split():
                 yield value
 
-    def get(self, section, option, default = ""):
+    def get(self, section, option, default = "", **kwargs):
         try:
-            return configparser.RawConfigParser.get(self, section, option)
+            return super().get(section = section, option = option, **kwargs)
         except configparser.NoSectionError:
             if section in ("core board_regs", "core comm_regs"):
                 return default
@@ -236,12 +232,12 @@ class Core(object):
             try:
                 self.block_bits = {4:2, 8:3, 16:4, 32:5}[self.blocks]
             except KeyError:
-                raise ValueError, "In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks)
+                raise ValueError("In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks))
             self.block_bit_max = self.block_bits - 1
         for subcore in cfg.getvalues(self.cfg_section, "subcores"):
             self.subcores.append(SubCore(subcore, self))
         if len(self.subcores) > self.blocks - 1:
-            raise ValueError, "In [{}]: number of subcores exceeds size of \"core blocks\"".format(self.cfg_section)
+            raise ValueError("In [{}]: number of subcores exceeds size of \"core blocks\"".format(self.cfg_section))
         self.module_name = cfg.get(self.cfg_section, "module name") or self.name
         self.dummy = cfg.get(self.cfg_section, "dummy")
         if self.dummy:
@@ -284,12 +280,12 @@ class Core(object):
         if self.blocks == 1 or self.subcores:
             return "CORE_ADDR_{core.upper_instance_name}".format(core=self)
         else:
-            return ",\n                ".join("CORE_ADDR_{core.upper_instance_name} + {core.addr_width}'h{0:04X}".format(i, core=self) for i in range(self.blocks)) 
+            return ",\n                ".join("CORE_ADDR_{core.upper_instance_name} + {core.addr_width}'h{0:04X}".format(i, core=self) for i in range(self.blocks))
 
     @property
     def reg_data_out(self):
         return "reg_read_data_" + self.instance_name
-        
+
     @property
     def comb_data_out(self):
         return "comb_read_data_" + self.instance_name
@@ -301,7 +297,7 @@ class Core(object):
     @property
     def pipe_data_out(self):
         return "pipe_read_data_" + self.instance_name
-        
+
     @property
     def mux_error_reg(self):
         return "error_" + self.instance_name if self.error_wire else "0"
@@ -309,7 +305,7 @@ class Core(object):
     @property
     def parameters(self):
         if self._parameters:
-            return "#( {} ) ".format(", ".join(".{} ({})".format(k, v) for k, v in self._parameters.iteritems()))
+            return "#( {} ) ".format(", ".join(".{} ({})".format(k, v) for k, v in self._parameters.items()))
         else:
             return ""
 
@@ -368,7 +364,7 @@ createInstance_template_generic = """\
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg          write_{core.instance_name} = 1'b0;
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg  [31: 0] write_data_{core.instance_name};
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg  [ 7: 0] addr_{core.instance_name};
-    
+
     always @(posedge sys_clk) begin
         select_{core.instance_name} <= enable_{core.instance_name} && sys_{core.bus_name}_cs;
         write_{core.instance_name} <= sys_{core.bus_name}_wr;
@@ -408,7 +404,7 @@ createInstance_template_multi_block = """\
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg           write_{core.instance_name} = 1'b0;
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg  [ 31: 0] write_data_{core.instance_name};
     (* SHREG_EXTRACT="NO" *) (* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg  [{core.block_bits}+7: 0] addr_{core.instance_name};
-    
+
     always @(posedge sys_clk) begin
         select_{core.instance_name} <= enable_{core.instance_name} && sys_{core.bus_name}_cs;
         write_{core.instance_name} <= sys_{core.bus_name}_wr;
@@ -528,7 +524,7 @@ module core_selector
 
 {insts}
 
-    
+
     //----------------------------------------------------------------
     // Output (Read Data) Multiplexer
     //----------------------------------------------------------------
@@ -545,13 +541,13 @@ module core_selector
         sys_{core.bus_name}_cs_dly2 <= sys_{core.bus_name}_cs_dly1;
         sys_{core.bus_name}_cs_dly3 <= sys_{core.bus_name}_cs_dly2;
     end
-    
+
     always @(posedge sys_clk) begin
         if (sys_{core.bus_name}_cs)      addr_core_num_dly1 <= addr_core_num;
         if (sys_{core.bus_name}_cs_dly1) addr_core_num_dly2 <= addr_core_num_dly1;
         if (sys_{core.bus_name}_cs_dly2) addr_core_num_dly3 <= addr_core_num_dly2;
     end
-    
+
     reg [31: 0] sys_read_data_mux;
     reg         sys_error_mux;
 
@@ -561,7 +557,7 @@ module core_selector
     always @(posedge sys_clk)
 
         if (sys_{core.bus_name}_cs_dly3)
-        
+
             case (addr_core_num_dly3)
 {muxes}
                 default: begin