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authorPaul Selkirk <paul@psgd.org>2018-09-11 18:55:54 -0400
committerPaul Selkirk <paul@psgd.org>2019-01-22 20:04:28 -0500
commit050237cf05b7bef2887a53b1dba1f6d95e2759ec (patch)
tree73bd113db46eeea1c5db969d0c5130dbba37cd95
parent1c4ba32f4190c0a4b501077225762598ba9d4821 (diff)
Track Joachim's latest keywrap core - unroll bank-switched memory into a number of core register blocks.
-rw-r--r--config/core.cfg3
-rwxr-xr-xconfig/core_config.py2
2 files changed, 3 insertions, 2 deletions
diff --git a/config/core.cfg b/config/core.cfg
index 12362c6..70b86ab 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -80,7 +80,7 @@ cores = mkmif
[project rsa]
# RSA signing and verification. This is as much as will fit on the
# Novena's Spartan-6 FPGA.
-cores = sha256 aes trng modexp
+cores = sha256 aes trng modexp mkmif
[project hsm]
# Make me one with everything, except we want two modexp cores for parallel CRT
@@ -333,6 +333,7 @@ vfiles =
[core keywrap]
# Joachim's experimental AES-keywrap core
requires = aes
+core blocks = 32
block memory = yes
error wire = yes
module name = keywrap
diff --git a/config/core_config.py b/config/core_config.py
index 4033279..d84f8f1 100755
--- a/config/core_config.py
+++ b/config/core_config.py
@@ -226,7 +226,7 @@ class Core(object):
self.block_max = self.blocks - 1
if self.blocks > 1:
try:
- self.block_bits = {4:2, 8:3, 16:4}[self.blocks]
+ self.block_bits = {4:2, 8:3, 16:4, 32:5}[self.blocks]
except KeyError:
raise ValueError, "In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks)
self.block_bit_max = self.block_bits - 1