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# Localize all the relative path awfulness in one variable.
CORE_TREE := $(abspath ../../..)
# Figure out what the native word size is on the build host, because
# the XiLinx tools care for some reason.
WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
# Parameters to xilinx.mk.
project ?= alpha_fmc_test
vendor = xilinx
family = artix7
part = xc7a200tfbg484-3
top_module = alpha_fmc_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
all: $(project).bit
# Verilog files that always go with builds on this platform.
vfiles = \
$(CORE_TREE)/platform/alpha/rtl/alpha_fmc_test.v \
$(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \
$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
$(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
include xilinx.mk
# 'clean' target collects files by project name, and we just broke that
# by adding configurations
junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \
*.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \
*.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \
*_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \
*_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \
*_summary.xml *_usage.xml
distclean: clean
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