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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:47:33 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:47:33 +0300 |
| commit | 8cd28d0fc12f0671ae3af89209de52a159d8cf19 (patch) | |
| tree | 7aee60c63fa75b88b1e047748342be1e8d09a1bb /build/Makefile | |
| parent | f8f86f9cfbd0ac73d2b0d3600e424b9c669cea59 (diff) | |
Added `include directories to Makefile
Diffstat (limited to 'build/Makefile')
| -rw-r--r-- | build/Makefile | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/build/Makefile b/build/Makefile index f573ace..5a6107d 100644 --- a/build/Makefile +++ b/build/Makefile @@ -16,7 +16,11 @@ part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf ?= ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf + +# verilog include directories {yes, XST wants them exactly this way in curly braces} +vlgincdir = {$(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode} + all: $(project).bit |