Renamed some modules, removed leftover debug code.

8 files changed, 23 insertions, 75 deletions

diff --git a/bench/tb_base_point_multiplier.v b/bench/tb_base_point_multiplier.v
index f4a60ae..b77b6e2 100644
--- a/bench/tb_base_point_multiplier.v
+++ b/bench/tb_base_point_multiplier.v
@@ -111,7 +111,7 @@ module tb_base_point_multiplier;
         //
         // UUT
         //
-    ed25519_multiplier uut
+    ed25519_base_point_multiplier uut
     (
         .clk        (clk),
         .rst_n      (rst_n),
diff --git a/rtl/ed25519_banks.v b/rtl/ed25519_banks_array.v
index 1b22c4b..eadce5e 100644
--- a/rtl/ed25519_banks.v
+++ b/rtl/ed25519_banks_array.v
@@ -1,8 +1,8 @@
 //------------------------------------------------------------------------------
 //
-// ed25519_banks.v
+// ed25519_banks_array.v
 // -----------------------------------------------------------------------------
-// Ed25519 Operand Banks
+// Ed25519 Operand Banks Array
 //
 // Authors: Pavel Shatov
 //
@@ -36,7 +36,7 @@
 //
 //------------------------------------------------------------------------------
 
-module ed25519_banks
+module ed25519_banks_array
 (
     input           clk,
     
@@ -70,7 +70,7 @@ module ed25519_banks
     assign src1_dout = !banks ? bank_lo1_dout : bank_hi1_dout;
     assign src2_dout = !banks ? bank_lo2_dout : bank_hi2_dout;
     
-    ed25519_bank bank_lo1
+    ed25519_operand_bank bank_operand_lo1
     (
         .clk     (clk),
         .a_addr  ({dst_operand, dst_addr}),
@@ -80,7 +80,7 @@ module ed25519_banks
         .b_out   (bank_lo1_dout)
     );
     
-    ed25519_bank bank_lo2
+    ed25519_operand_bank bank_operand_lo2
     (
         .clk     (clk),
         .a_addr  ({dst_operand, dst_addr}),
@@ -90,7 +90,7 @@ module ed25519_banks
         .b_out   (bank_lo2_dout)
     );
 
-    ed25519_bank bank_hi1
+    ed25519_operand_bank bank_operand_hi1
     (
         .clk     (clk),
         .a_addr  ({dst_operand, dst_addr}),
@@ -100,7 +100,7 @@ module ed25519_banks
         .b_out   (bank_hi1_dout)
     );
 
-    ed25519_bank bank_hi2
+    ed25519_operand_bank bank_operand_hi2
     (
         .clk     (clk),
         .a_addr  ({dst_operand, dst_addr}),
diff --git a/rtl/ed25519_multiplier.v b/rtl/ed25519_base_point_multiplier.v
index 31a4b18..ddde3c4 100644
--- a/rtl/ed25519_multiplier.v
+++ b/rtl/ed25519_base_point_multiplier.v
@@ -1,6 +1,6 @@
 //------------------------------------------------------------------------------
 //
-// ed25519_multiplier.v
+// ed25519_base_point_multiplier.v
 // -----------------------------------------------------------------------------
 // Ed25519 base point scalar multiplier.
 //
@@ -36,7 +36,7 @@
 //
 //------------------------------------------------------------------------------
 
-module ed25519_multiplier
+module ed25519_base_point_multiplier
 (
     clk, rst_n,
     ena, rdy,
@@ -50,7 +50,7 @@ module ed25519_multiplier
     //
     // Microcode Header
     //
-`include "ed25519_uop.v"
+`include "ed25519_uop.vh"
     
 
     //
@@ -256,19 +256,6 @@ module ed25519_multiplier
     end
 
 
-	//
-	// Debug
-	//
-    wire debug_dump_now = fsm_state == FSM_STATE_OUTPUT_TRIG;
-	
-	reg [6:0] debug_dump_addr1 = {1'bX, UOP_OPERAND_INVERT_R1};
-	reg [6:0] debug_dump_addr2 = {1'b0, UOP_OPERAND_CYCLE_R0_X};
-	reg [6:0] debug_dump_addr3 = {1'b0, UOP_OPERAND_CYCLE_R0_Y};
-	reg [6:0] debug_dump_addr4 = {1'bX, UOP_OPERAND_CYCLE_R0_T};
-	reg [6:0] debug_dump_addr5 = {1'bX, UOP_OPERAND_CYCLE_R1_X};
-	reg [6:0] debug_dump_addr6 = {1'bX, UOP_OPERAND_CYCLE_R1_Y};
-	reg [6:0] debug_dump_addr7 = {1'bX, UOP_OPERAND_CYCLE_R1_Z};
-	reg [6:0] debug_dump_addr8 = {1'bX, UOP_OPERAND_CYCLE_R1_T};
 
     //
     // Worker
@@ -278,20 +265,10 @@ module ed25519_multiplier
     wire worker_handle_sign  = fsm_state == FSM_STATE_HANDLE_SIGN_WAIT;
     wire worker_output_now   = fsm_state == FSM_STATE_OUTPUT_WAIT;
     
-    ed25519_worker uop_worker
+    ed25519_uop_worker uop_worker
     (
         .clk        (clk),
         .rst_n      (rst_n),
-        .debug_dump_now		(debug_dump_now),
-
-        .debug_dump_addr1	(debug_dump_addr1),
-        .debug_dump_addr2	(debug_dump_addr2),
-        .debug_dump_addr3	(debug_dump_addr3),
-        .debug_dump_addr4	(debug_dump_addr4),
-        .debug_dump_addr5	(debug_dump_addr5),
-        .debug_dump_addr6	(debug_dump_addr6),
-        .debug_dump_addr7	(debug_dump_addr7),
-        .debug_dump_addr8	(debug_dump_addr8),
 		  
         .ena            (worker_trig),
         .rdy            (worker_done),
diff --git a/rtl/ed25519_core.v b/rtl/ed25519_core_top.v
index 90d12c5..a217c75 100644
--- a/rtl/ed25519_core.v
+++ b/rtl/ed25519_core_top.v
@@ -32,7 +32,7 @@
 
 `timescale 1ns / 1ps
 
-module ed25519_core
+module ed25519_core_top
 (
     input    wire        clk,
     input    wire        rst_n,
@@ -110,7 +110,7 @@ module ed25519_core
     always @(posedge clk) next_dly <= next;
     wire next_trig = next && !next_dly;
 
-    ed25519_multiplier ed25519_multiplier_inst
+    ed25519_base_point_multiplier ed25519_base_point_multiplier_inst
     (
         .clk        (clk),
         .rst_n      (rst_n),
diff --git a/rtl/ed25519_microcode.v b/rtl/ed25519_microcode_rom.v
index ec36e3f..acce4fd 100644
--- a/rtl/ed25519_microcode.v
+++ b/rtl/ed25519_microcode_rom.v
@@ -30,14 +30,14 @@
 //
 //======================================================================
 
-module ed25519_microcode
+module ed25519_microcode_rom
 (
     input  wire 	                 clk,
     input  wire [UOP_ADDR_WIDTH-1:0] addr,
     output reg  [UOP_DATA_WIDTH-1:0] data
 );
 
-`include "ed25519_uop.v"
+`include "ed25519_uop.vh"
 
     always @(posedge clk)
         //
diff --git a/rtl/ed25519_bank.v b/rtl/ed25519_operand_bank.v
index 81984f3..21ebbfc 100644
--- a/rtl/ed25519_bank.v
+++ b/rtl/ed25519_operand_bank.v
@@ -32,7 +32,7 @@
 
 `timescale 1ns / 1ps
 
-module ed25519_bank
+module ed25519_operand_bank
 (
     input               clk,
 
diff --git a/rtl/ed25519_uop.v b/rtl/ed25519_uop.vh
index 12b9e10..12b9e10 100644
--- a/rtl/ed25519_uop.v
+++ b/rtl/ed25519_uop.vh
diff --git a/rtl/ed25519_worker.v b/rtl/ed25519_uop_worker.v
index be8152e..244ff97 100644
--- a/rtl/ed25519_worker.v
+++ b/rtl/ed25519_uop_worker.v
@@ -36,7 +36,7 @@
 //
 //------------------------------------------------------------------------------
 
-module ed25519_worker
+module ed25519_uop_worker
 (
     clk, rst_n,
     ena, rdy,
@@ -44,23 +44,14 @@ module ed25519_worker
     final_reduce,
     handle_sign,
     output_now,
-    y_addr, y_dout, y_wren,
-    debug_dump_now,
-    debug_dump_addr1,
-    debug_dump_addr2,
-    debug_dump_addr3,
-    debug_dump_addr4,
-    debug_dump_addr5,
-    debug_dump_addr6,
-    debug_dump_addr7,
-    debug_dump_addr8
+    y_addr, y_dout, y_wren
 );
 
 
     //
     // Microcode Header
     //
-`include "ed25519_uop.v"
+`include "ed25519_uop.vh"
 
 
     //
@@ -82,16 +73,6 @@ module ed25519_worker
     output  [31: 0] y_dout;
     output          y_wren;
     
-    input debug_dump_now;
-    input [6:0] debug_dump_addr1;
-    input [6:0] debug_dump_addr2;
-    input [6:0] debug_dump_addr3;
-    input [6:0] debug_dump_addr4;
-    input [6:0] debug_dump_addr5;
-    input [6:0] debug_dump_addr6;
-    input [6:0] debug_dump_addr7;
-    input [6:0] debug_dump_addr8;
-
     
     //
     // Constants
@@ -130,7 +111,7 @@ module ed25519_worker
     wire uop_data_opcode_is_add  = uop_data_opcode[1];
     wire uop_data_opcode_is_copy = uop_data_opcode[0];
     
-    ed25519_microcode microcode
+    ed25519_microcode_rom microcode_rom
     (
         .clk    (clk),
         .addr   (uop_addr),
@@ -349,7 +330,7 @@ module ed25519_worker
     wire    [31:0]  banks_src1_dout;
     wire    [31:0]  banks_src2_dout;    
     
-    ed25519_banks banks
+    ed25519_banks_array banks_array
     (
         .clk            (clk),
     
@@ -368,17 +349,7 @@ module ed25519_worker
         .src1_dout      (banks_src1_dout),
         .src2_dout      (banks_src2_dout),
     
-        .dst_din        (banks_dst_din),
-        
-        .debug_dump_now(debug_dump_now),
-        .debug_dump_addr1(debug_dump_addr1),
-        .debug_dump_addr2(debug_dump_addr2),
-        .debug_dump_addr3(debug_dump_addr3),
-        .debug_dump_addr4(debug_dump_addr4),
-        .debug_dump_addr5(debug_dump_addr5),
-        .debug_dump_addr6(debug_dump_addr6),
-        .debug_dump_addr7(debug_dump_addr7),
-        .debug_dump_addr8(debug_dump_addr8)
+        .dst_din        (banks_dst_din)
     );
     
     assign mw_mover_x_din   = banks_src1_dout;