From 427794f1880bdb05f301d606df728c01eb3ebd25 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 15 Oct 2018 21:27:03 +0300 Subject: Renamed some modules, removed leftover debug code. --- bench/tb_base_point_multiplier.v | 2 +- rtl/ed25519_bank.v | 140 --------- rtl/ed25519_banks.v | 119 -------- rtl/ed25519_banks_array.v | 119 ++++++++ rtl/ed25519_base_point_multiplier.v | 306 ++++++++++++++++++++ rtl/ed25519_core.v | 150 ---------- rtl/ed25519_core_top.v | 150 ++++++++++ rtl/ed25519_microcode.v | 426 ---------------------------- rtl/ed25519_microcode_rom.v | 426 ++++++++++++++++++++++++++++ rtl/ed25519_multiplier.v | 329 --------------------- rtl/ed25519_operand_bank.v | 140 +++++++++ rtl/ed25519_uop.v | 128 --------- rtl/ed25519_uop.vh | 128 +++++++++ rtl/ed25519_uop_worker.v | 520 ++++++++++++++++++++++++++++++++++ rtl/ed25519_worker.v | 549 ------------------------------------ 15 files changed, 1790 insertions(+), 1842 deletions(-) delete mode 100644 rtl/ed25519_bank.v delete mode 100644 rtl/ed25519_banks.v create mode 100644 rtl/ed25519_banks_array.v create mode 100644 rtl/ed25519_base_point_multiplier.v delete mode 100644 rtl/ed25519_core.v create mode 100644 rtl/ed25519_core_top.v delete mode 100644 rtl/ed25519_microcode.v create mode 100644 rtl/ed25519_microcode_rom.v delete mode 100644 rtl/ed25519_multiplier.v create mode 100644 rtl/ed25519_operand_bank.v delete mode 100644 rtl/ed25519_uop.v create mode 100644 rtl/ed25519_uop.vh create mode 100644 rtl/ed25519_uop_worker.v delete mode 100644 rtl/ed25519_worker.v diff --git a/bench/tb_base_point_multiplier.v b/bench/tb_base_point_multiplier.v index f4a60ae..b77b6e2 100644 --- a/bench/tb_base_point_multiplier.v +++ b/bench/tb_base_point_multiplier.v @@ -111,7 +111,7 @@ module tb_base_point_multiplier; // // UUT // - ed25519_multiplier uut + ed25519_base_point_multiplier uut ( .clk (clk), .rst_n (rst_n), diff --git a/rtl/ed25519_bank.v b/rtl/ed25519_bank.v deleted file mode 100644 index 81984f3..0000000 --- a/rtl/ed25519_bank.v +++ /dev/null @@ -1,140 +0,0 @@ -//====================================================================== -// -// Copyright (c) 2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -`timescale 1ns / 1ps - -module ed25519_bank -( - input clk, - - input [ 9-1:0] a_addr, - input a_wr, - input [32-1:0] a_in, - - input [ 9-1:0] b_addr, - output [32-1:0] b_out -); - - - // - // BRAM - // - reg [31:0] bram[0:64*8-1]; - - - // - // Initialization - // - initial begin - // - // CONST_ZERO - // - bram[ 0*8 + 7] = 32'h00000000; - bram[ 0*8 + 6] = 32'h00000000; - bram[ 0*8 + 5] = 32'h00000000; - bram[ 0*8 + 4] = 32'h00000000; - bram[ 0*8 + 3] = 32'h00000000; - bram[ 0*8 + 2] = 32'h00000000; - bram[ 0*8 + 1] = 32'h00000000; - bram[ 0*8 + 0] = 32'h00000000; - // - // CONST_ONE - // - bram[ 1*8 + 7] = 32'h00000000; - bram[ 1*8 + 6] = 32'h00000000; - bram[ 1*8 + 5] = 32'h00000000; - bram[ 1*8 + 4] = 32'h00000000; - bram[ 1*8 + 3] = 32'h00000000; - bram[ 1*8 + 2] = 32'h00000000; - bram[ 1*8 + 1] = 32'h00000000; - bram[ 1*8 + 0] = 32'h00000001; - // - // G_X - // - bram[14*8 + 7] = 32'h216936d3; - bram[14*8 + 6] = 32'hcd6e53fe; - bram[14*8 + 5] = 32'hc0a4e231; - bram[14*8 + 4] = 32'hfdd6dc5c; - bram[14*8 + 3] = 32'h692cc760; - bram[14*8 + 2] = 32'h9525a7b2; - bram[14*8 + 1] = 32'hc9562d60; - bram[14*8 + 0] = 32'h8f25d51a; - // - // G_Y - // - bram[15*8 + 7] = 32'h66666666; - bram[15*8 + 6] = 32'h66666666; - bram[15*8 + 5] = 32'h66666666; - bram[15*8 + 4] = 32'h66666666; - bram[15*8 + 3] = 32'h66666666; - bram[15*8 + 2] = 32'h66666666; - bram[15*8 + 1] = 32'h66666666; - bram[15*8 + 0] = 32'h66666658; - // - // G_T - // - bram[16*8 + 7] = 32'h67875f0f; - bram[16*8 + 6] = 32'hd78b7665; - bram[16*8 + 5] = 32'h66ea4e8e; - bram[16*8 + 4] = 32'h64abe37d; - bram[16*8 + 3] = 32'h20f09f80; - bram[16*8 + 2] = 32'h775152f5; - bram[16*8 + 1] = 32'h6dde8ab3; - bram[16*8 + 0] = 32'ha5b7dda3; - end - - - // - // Output Register - // - reg [32-1:0] bram_reg_b; - - assign b_out = bram_reg_b; - - - // - // Write Port A - // - always @(posedge clk) - // - if (a_wr) bram[a_addr] <= a_in; - - - // - // Read Port B - // - always @(posedge clk) - // - bram_reg_b <= bram[b_addr]; - - -endmodule diff --git a/rtl/ed25519_banks.v b/rtl/ed25519_banks.v deleted file mode 100644 index 1b22c4b..0000000 --- a/rtl/ed25519_banks.v +++ /dev/null @@ -1,119 +0,0 @@ -//------------------------------------------------------------------------------ -// -// ed25519_banks.v -// ----------------------------------------------------------------------------- -// Ed25519 Operand Banks -// -// Authors: Pavel Shatov -// -// Copyright (c) 2018, NORDUnet A/S -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//------------------------------------------------------------------------------ - -module ed25519_banks -( - input clk, - - input banks, // 0: LO -> HI, 1: HI -> LO - - input [ 5:0] src1_operand, - input [ 5:0] src2_operand, - input [ 5:0] dst_operand, - - input [ 2:0] src1_addr, - input [ 2:0] src2_addr, - input [ 2:0] dst_addr, - - input dst_wren, - - output [31:0] src1_dout, - output [31:0] src2_dout, - - input [31:0] dst_din -); - - - // - // Banks - // - wire [31:0] bank_lo1_dout; - wire [31:0] bank_lo2_dout; - wire [31:0] bank_hi1_dout; - wire [31:0] bank_hi2_dout; - - assign src1_dout = !banks ? bank_lo1_dout : bank_hi1_dout; - assign src2_dout = !banks ? bank_lo2_dout : bank_hi2_dout; - - ed25519_bank bank_lo1 - ( - .clk (clk), - .a_addr ({dst_operand, dst_addr}), - .a_wr (dst_wren & banks), - .a_in (dst_din), - .b_addr ({src1_operand, src1_addr}), - .b_out (bank_lo1_dout) - ); - - ed25519_bank bank_lo2 - ( - .clk (clk), - .a_addr ({dst_operand, dst_addr}), - .a_wr (dst_wren & banks), - .a_in (dst_din), - .b_addr ({src2_operand, src2_addr}), - .b_out (bank_lo2_dout) - ); - - ed25519_bank bank_hi1 - ( - .clk (clk), - .a_addr ({dst_operand, dst_addr}), - .a_wr (dst_wren & ~banks), - .a_in (dst_din), - .b_addr ({src1_operand, src1_addr}), - .b_out (bank_hi1_dout) - ); - - ed25519_bank bank_hi2 - ( - .clk (clk), - .a_addr ({dst_operand, dst_addr}), - .a_wr (dst_wren & ~banks), - .a_in (dst_din), - .b_addr ({src2_operand, src2_addr}), - .b_out (bank_hi2_dout) - ); - - -endmodule - - -//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_banks_array.v b/rtl/ed25519_banks_array.v new file mode 100644 index 0000000..eadce5e --- /dev/null +++ b/rtl/ed25519_banks_array.v @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// ed25519_banks_array.v +// ----------------------------------------------------------------------------- +// Ed25519 Operand Banks Array +// +// Authors: Pavel Shatov +// +// Copyright (c) 2018, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module ed25519_banks_array +( + input clk, + + input banks, // 0: LO -> HI, 1: HI -> LO + + input [ 5:0] src1_operand, + input [ 5:0] src2_operand, + input [ 5:0] dst_operand, + + input [ 2:0] src1_addr, + input [ 2:0] src2_addr, + input [ 2:0] dst_addr, + + input dst_wren, + + output [31:0] src1_dout, + output [31:0] src2_dout, + + input [31:0] dst_din +); + + + // + // Banks + // + wire [31:0] bank_lo1_dout; + wire [31:0] bank_lo2_dout; + wire [31:0] bank_hi1_dout; + wire [31:0] bank_hi2_dout; + + assign src1_dout = !banks ? bank_lo1_dout : bank_hi1_dout; + assign src2_dout = !banks ? bank_lo2_dout : bank_hi2_dout; + + ed25519_operand_bank bank_operand_lo1 + ( + .clk (clk), + .a_addr ({dst_operand, dst_addr}), + .a_wr (dst_wren & banks), + .a_in (dst_din), + .b_addr ({src1_operand, src1_addr}), + .b_out (bank_lo1_dout) + ); + + ed25519_operand_bank bank_operand_lo2 + ( + .clk (clk), + .a_addr ({dst_operand, dst_addr}), + .a_wr (dst_wren & banks), + .a_in (dst_din), + .b_addr ({src2_operand, src2_addr}), + .b_out (bank_lo2_dout) + ); + + ed25519_operand_bank bank_operand_hi1 + ( + .clk (clk), + .a_addr ({dst_operand, dst_addr}), + .a_wr (dst_wren & ~banks), + .a_in (dst_din), + .b_addr ({src1_operand, src1_addr}), + .b_out (bank_hi1_dout) + ); + + ed25519_operand_bank bank_operand_hi2 + ( + .clk (clk), + .a_addr ({dst_operand, dst_addr}), + .a_wr (dst_wren & ~banks), + .a_in (dst_din), + .b_addr ({src2_operand, src2_addr}), + .b_out (bank_hi2_dout) + ); + + +endmodule + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_base_point_multiplier.v b/rtl/ed25519_base_point_multiplier.v new file mode 100644 index 0000000..ddde3c4 --- /dev/null +++ b/rtl/ed25519_base_point_multiplier.v @@ -0,0 +1,306 @@ +//------------------------------------------------------------------------------ +// +// ed25519_base_point_multiplier.v +// ----------------------------------------------------------------------------- +// Ed25519 base point scalar multiplier. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2018, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module ed25519_base_point_multiplier +( + clk, rst_n, + ena, rdy, + k_addr, qy_addr, + qy_wren, + k_din, + qy_dout +); + + + // + // Microcode Header + // +`include "ed25519_uop.vh" + + + // + // Ports + // + input clk; // system clock + input rst_n; // active-low async reset + + input ena; // enable input + output rdy; // ready output + + output [ 2:0] k_addr; // + output [ 2:0] qy_addr; // + output qy_wren; // + input [31:0] k_din; // + output [31:0] qy_dout; // + + + // + // FSM + // + localparam [4:0] FSM_STATE_IDLE = 5'd00; + localparam [4:0] FSM_STATE_PREPARE_TRIG = 5'd01; + localparam [4:0] FSM_STATE_PREPARE_WAIT = 5'd02; + localparam [4:0] FSM_STATE_BEFORE_ROUND_TRIG = 5'd03; + localparam [4:0] FSM_STATE_BEFORE_ROUND_WAIT = 5'd04; + localparam [4:0] FSM_STATE_DURING_ROUND_TRIG = 5'd05; + localparam [4:0] FSM_STATE_DURING_ROUND_WAIT = 5'd06; + localparam [4:0] FSM_STATE_AFTER_ROUND_TRIG = 5'd07; + localparam [4:0] FSM_STATE_AFTER_ROUND_WAIT = 5'd08; + localparam [4:0] FSM_STATE_BEFORE_INVERT_TRIG = 5'd09; + localparam [4:0] FSM_STATE_BEFORE_INVERT_WAIT = 5'd10; + localparam [4:0] FSM_STATE_DURING_INVERT_TRIG = 5'd11; + localparam [4:0] FSM_STATE_DURING_INVERT_WAIT = 5'd12; + localparam [4:0] FSM_STATE_AFTER_INVERT_TRIG = 5'd13; + localparam [4:0] FSM_STATE_AFTER_INVERT_WAIT = 5'd14; + localparam [4:0] FSM_STATE_FINAL_REDUCE_TRIG = 5'd15; + localparam [4:0] FSM_STATE_FINAL_REDUCE_WAIT = 5'd16; + localparam [4:0] FSM_STATE_HANDLE_SIGN_TRIG = 5'd17; + localparam [4:0] FSM_STATE_HANDLE_SIGN_WAIT = 5'd18; + localparam [4:0] FSM_STATE_OUTPUT_TRIG = 5'd19; + localparam [4:0] FSM_STATE_OUTPUT_WAIT = 5'd20; + localparam [4:0] FSM_STATE_DONE = 5'd31; + + reg [4:0] fsm_state = FSM_STATE_IDLE; + reg [4:0] fsm_state_next; + + + // + // Round Counter + // + reg [7:0] bit_counter; + wire [7:0] bit_counter_max = 8'hFF; // 255 + wire [7:0] bit_counter_zero = 8'h00; // 0 + wire [7:0] bit_counter_next = + (bit_counter < bit_counter_max) ? bit_counter + 1'b1 : bit_counter_zero; + + assign k_addr = bit_counter[7:5]; + + + // + // Worker Trigger Logic + // + reg worker_trig = 1'b0; + wire worker_done; + + wire fsm_wait_done = !worker_trig && worker_done; + + always @(posedge clk or negedge rst_n) + // + if (rst_n == 1'b0) worker_trig <= 1'b0; + else case (fsm_state) + FSM_STATE_PREPARE_TRIG, + FSM_STATE_BEFORE_ROUND_TRIG, + FSM_STATE_DURING_ROUND_TRIG, + FSM_STATE_AFTER_ROUND_TRIG, + FSM_STATE_BEFORE_INVERT_TRIG, + FSM_STATE_DURING_INVERT_TRIG, + FSM_STATE_AFTER_INVERT_TRIG, + FSM_STATE_FINAL_REDUCE_TRIG, + FSM_STATE_HANDLE_SIGN_TRIG, + FSM_STATE_OUTPUT_TRIG: worker_trig <= 1'b1; + default: worker_trig <= 1'b0; + endcase + + + // + // Round Counter Increment Logic + // + always @(posedge clk) + // + case (fsm_state_next) + FSM_STATE_PREPARE_TRIG: bit_counter <= bit_counter_zero; + FSM_STATE_AFTER_ROUND_TRIG: bit_counter <= bit_counter_next; + endcase + + + // + // Final Round Detection Logic + // + wire [ 3: 0] fsm_state_after_round = (bit_counter != bit_counter_zero) ? + FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_BEFORE_INVERT_TRIG; + + + // + // K Latch + // + reg [31:0] k_din_shreg; + + wire [4:0] k_bit_index = bit_counter[4:0]; + + always @(posedge clk) + // + if (fsm_state_next == FSM_STATE_BEFORE_ROUND_TRIG) + // + if (k_bit_index == 5'd0) + // + case (k_addr) + 3'd0: k_din_shreg <= {k_din[31:3], 3'b000}; + 3'd7: k_din_shreg <= {2'b01, k_din[29:0]}; + default: k_din_shreg <= k_din; + endcase + // + else k_din_shreg <= {k_din_shreg[0], k_din_shreg[31:1]}; + + + // + // Worker Offset Logic + // + reg [UOP_ADDR_WIDTH-1:0] worker_offset; + + always @(posedge clk) + // + case (fsm_state) + FSM_STATE_PREPARE_TRIG: worker_offset <= UOP_OFFSET_PREPARE; + FSM_STATE_BEFORE_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_BEFORE_ROUND_K1 : UOP_OFFSET_BEFORE_ROUND_K0; + FSM_STATE_DURING_ROUND_TRIG: worker_offset <= UOP_OFFSET_DURING_ROUND; + FSM_STATE_AFTER_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_AFTER_ROUND_K1 : UOP_OFFSET_AFTER_ROUND_K0; + FSM_STATE_BEFORE_INVERT_TRIG: worker_offset <= UOP_OFFSET_BEFORE_INVERSION; + FSM_STATE_DURING_INVERT_TRIG: worker_offset <= UOP_OFFSET_DURING_INVERSION; + FSM_STATE_AFTER_INVERT_TRIG: worker_offset <= UOP_OFFSET_AFTER_INVERSION; + FSM_STATE_FINAL_REDUCE_TRIG: worker_offset <= UOP_OFFSET_FINAL_REDUCTION; + FSM_STATE_HANDLE_SIGN_TRIG: worker_offset <= UOP_OFFSET_HANDLE_SIGN; + FSM_STATE_OUTPUT_TRIG: worker_offset <= UOP_OFFSET_OUTPUT; + default: worker_offset <= {UOP_ADDR_WIDTH{1'bX}}; + endcase + + + // + // FSM Process + // + always @(posedge clk or negedge rst_n) + // + if (rst_n == 1'b0) fsm_state <= FSM_STATE_IDLE; + else fsm_state <= fsm_state_next; + + + // + // FSM Transition Logic + // + always @* begin + // + fsm_state_next = FSM_STATE_IDLE; + // + case (fsm_state) + + FSM_STATE_IDLE: fsm_state_next = ena ? FSM_STATE_PREPARE_TRIG : FSM_STATE_IDLE; + + FSM_STATE_PREPARE_TRIG: fsm_state_next = FSM_STATE_PREPARE_WAIT; + FSM_STATE_PREPARE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_PREPARE_WAIT; + + FSM_STATE_BEFORE_ROUND_TRIG: fsm_state_next = FSM_STATE_BEFORE_ROUND_WAIT; + FSM_STATE_BEFORE_ROUND_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DURING_ROUND_TRIG : FSM_STATE_BEFORE_ROUND_WAIT; + + FSM_STATE_DURING_ROUND_TRIG: fsm_state_next = FSM_STATE_DURING_ROUND_WAIT; + FSM_STATE_DURING_ROUND_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_ROUND_TRIG : FSM_STATE_DURING_ROUND_WAIT; + + FSM_STATE_AFTER_ROUND_TRIG: fsm_state_next = FSM_STATE_AFTER_ROUND_WAIT; + FSM_STATE_AFTER_ROUND_WAIT: fsm_state_next = fsm_wait_done ? fsm_state_after_round : FSM_STATE_AFTER_ROUND_WAIT; + + FSM_STATE_BEFORE_INVERT_TRIG: fsm_state_next = FSM_STATE_BEFORE_INVERT_WAIT; + FSM_STATE_BEFORE_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DURING_INVERT_TRIG : FSM_STATE_BEFORE_INVERT_WAIT; + + FSM_STATE_DURING_INVERT_TRIG: fsm_state_next = FSM_STATE_DURING_INVERT_WAIT; + FSM_STATE_DURING_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_INVERT_TRIG : FSM_STATE_DURING_INVERT_WAIT; + + FSM_STATE_AFTER_INVERT_TRIG: fsm_state_next = FSM_STATE_AFTER_INVERT_WAIT; + FSM_STATE_AFTER_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_FINAL_REDUCE_TRIG : FSM_STATE_AFTER_INVERT_WAIT; + + FSM_STATE_FINAL_REDUCE_TRIG: fsm_state_next = FSM_STATE_FINAL_REDUCE_WAIT; + FSM_STATE_FINAL_REDUCE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_HANDLE_SIGN_TRIG : FSM_STATE_FINAL_REDUCE_WAIT; + + FSM_STATE_HANDLE_SIGN_TRIG: fsm_state_next = FSM_STATE_HANDLE_SIGN_WAIT; + FSM_STATE_HANDLE_SIGN_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_OUTPUT_TRIG : FSM_STATE_HANDLE_SIGN_WAIT; + + FSM_STATE_OUTPUT_TRIG: fsm_state_next = FSM_STATE_OUTPUT_WAIT; + FSM_STATE_OUTPUT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DONE : FSM_STATE_OUTPUT_WAIT; + + FSM_STATE_DONE: fsm_state_next = FSM_STATE_IDLE; + + endcase + // + end + + + + // + // Worker + // + + wire worker_final_reduce = fsm_state == FSM_STATE_FINAL_REDUCE_WAIT; + wire worker_handle_sign = fsm_state == FSM_STATE_HANDLE_SIGN_WAIT; + wire worker_output_now = fsm_state == FSM_STATE_OUTPUT_WAIT; + + ed25519_uop_worker uop_worker + ( + .clk (clk), + .rst_n (rst_n), + + .ena (worker_trig), + .rdy (worker_done), + .uop_offset (worker_offset), + .final_reduce (worker_final_reduce), + .handle_sign (worker_handle_sign), + .output_now (worker_output_now), + + .y_addr (qy_addr), + .y_dout (qy_dout), + .y_wren (qy_wren) + ); + + + // + // Ready Flag Logic + // + reg rdy_reg = 1'b1; + assign rdy = rdy_reg; + + always @(posedge clk or negedge rst_n) + // + if (rst_n == 1'b0) rdy_reg <= 1'b1; + else case (fsm_state) + FSM_STATE_IDLE: if (ena) rdy_reg <= 1'b0; + FSM_STATE_DONE: rdy_reg <= 1'b1; + endcase + + +endmodule + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_core.v b/rtl/ed25519_core.v deleted file mode 100644 index 90d12c5..0000000 --- a/rtl/ed25519_core.v +++ /dev/null @@ -1,150 +0,0 @@ -//====================================================================== -// -// Copyright (c) 2018, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -`timescale 1ns / 1ps - -module ed25519_core -( - input wire clk, - input wire rst_n, - - input wire next, - output wire valid, - - input wire bus_cs, - input wire bus_we, - input wire [ 3:0] bus_addr, - input wire [31:0] bus_data_wr, - output wire [31:0] bus_data_rd -); - - - // - // Memory Banks - // - localparam [0:0] BUS_ADDR_BANK_K = 1'b0; - localparam [0:0] BUS_ADDR_BANK_QY = 1'b1; - - wire [0:0] bus_addr_upper = bus_addr[3:3]; - wire [2:0] bus_addr_lower = bus_addr[2:0]; - - - // - // Memories - // - wire [31:0] user_bram_k_rw_dout; - wire [31:0] user_bram_qy_ro_dout; - - wire [31:0] user_bram_k_rw_din; - - wire [ 2:0] core_bram_k_ro_addr; - wire [ 2:0] core_bram_qy_rw_addr; - - wire core_bram_qy_rw_wren; - - wire [31:0] core_bram_k_ro_dout; - wire [31:0] core_bram_qy_rw_dout_unused; - - wire [31:0] core_bram_qy_rw_din; - - assign user_bram_k_rw_din = bus_data_wr; - assign user_bram_k_rw_wren = bus_cs && bus_we && (bus_addr_upper == BUS_ADDR_BANK_K); - - bram_1rw_1ro_readfirst # - ( - .MEM_WIDTH(32), - .MEM_ADDR_BITS(3) - ) - bram_k - ( .clk(clk), - .a_addr(bus_addr_lower), .a_out(user_bram_k_rw_dout), .a_wr(user_bram_k_rw_wren), .a_in(user_bram_k_rw_din), - .b_addr(core_bram_k_ro_addr), .b_out(core_bram_k_ro_dout) - ); - - bram_1rw_1ro_readfirst # - ( - .MEM_WIDTH(32), - .MEM_ADDR_BITS(3) - ) - bram_qy - ( - .clk(clk), - .a_addr(core_bram_qy_rw_addr), .a_out(core_bram_qy_rw_dout_unused), .a_wr(core_bram_qy_rw_wren), .a_in(core_bram_qy_rw_din), - .b_addr(bus_addr_lower), .b_out(user_bram_qy_ro_dout) - ); - - - // - // Curve Base Point Multiplier - // - reg next_dly; - always @(posedge clk) next_dly <= next; - wire next_trig = next && !next_dly; - - ed25519_multiplier ed25519_multiplier_inst - ( - .clk (clk), - .rst_n (rst_n), - - .ena (next_trig), - .rdy (valid), - - .k_addr (core_bram_k_ro_addr), - .qy_addr (core_bram_qy_rw_addr), - - .qy_wren (core_bram_qy_rw_wren), - - .k_din (core_bram_k_ro_dout), - .qy_dout (core_bram_qy_rw_din) - ); - - - // - // Output Selector - // - reg [0:0] bus_addr_upper_dly; - always @(posedge clk) bus_addr_upper_dly <= bus_addr_upper; - - reg [31: 0] bus_data_rd_mux; - assign bus_data_rd = bus_data_rd_mux; - - always @(*) - // - case (bus_addr_upper_dly) - // - BUS_ADDR_BANK_K: bus_data_rd_mux = user_bram_k_rw_dout; - BUS_ADDR_BANK_QY: bus_data_rd_mux = user_bram_qy_ro_dout; - // - endcase - - -endmodule diff --git a/rtl/ed25519_core_top.v b/rtl/ed25519_core_top.v new file mode 100644 index 0000000..a217c75 --- /dev/null +++ b/rtl/ed25519_core_top.v @@ -0,0 +1,150 @@ +//====================================================================== +// +// Copyright (c) 2018, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +`timescale 1ns / 1ps + +module ed25519_core_top +( + input wire clk, + input wire rst_n, + + input wire next, + output wire valid, + + input wire bus_cs, + input wire bus_we, + input wire [ 3:0] bus_addr, + input wire [31:0] bus_data_wr, + output wire [31:0] bus_data_rd +); + + + // + // Memory Banks + // + localparam [0:0] BUS_ADDR_BANK_K = 1'b0; + localparam [0:0] BUS_ADDR_BANK_QY = 1'b1; + + wire [0:0] bus_addr_upper = bus_addr[3:3]; + wire [2:0] bus_addr_lower = bus_addr[2:0]; + + + // + // Memories + // + wire [31:0] user_bram_k_rw_dout; + wire [31:0] user_bram_qy_ro_dout; + + wire [31:0] user_bram_k_rw_din; + + wire [ 2:0] core_bram_k_ro_addr; + wire [ 2:0] core_bram_qy_rw_addr; + + wire core_bram_qy_rw_wren; + + wire [31:0] core_bram_k_ro_dout; + wire [31:0] core_bram_qy_rw_dout_unused; + + wire [31:0] core_bram_qy_rw_din; + + assign user_bram_k_rw_din = bus_data_wr; + assign user_bram_k_rw_wren = bus_cs && bus_we && (bus_addr_upper == BUS_ADDR_BANK_K); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH(32), + .MEM_ADDR_BITS(3) + ) + bram_k + ( .clk(clk), + .a_addr(bus_addr_lower), .a_out(user_bram_k_rw_dout), .a_wr(user_bram_k_rw_wren), .a_in(user_bram_k_rw_din), + .b_addr(core_bram_k_ro_addr), .b_out(core_bram_k_ro_dout) + ); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH(32), + .MEM_ADDR_BITS(3) + ) + bram_qy + ( + .clk(clk), + .a_addr(core_bram_qy_rw_addr), .a_out(core_bram_qy_rw_dout_unused), .a_wr(core_bram_qy_rw_wren), .a_in(core_bram_qy_rw_din), + .b_addr(bus_addr_lower), .b_out(user_bram_qy_ro_dout) + ); + + + // + // Curve Base Point Multiplier + // + reg next_dly; + always @(posedge clk) next_dly <= next; + wire next_trig = next && !next_dly; + + ed25519_base_point_multiplier ed25519_base_point_multiplier_inst + ( + .clk (clk), + .rst_n (rst_n), + + .ena (next_trig), + .rdy (valid), + + .k_addr (core_bram_k_ro_addr), + .qy_addr (core_bram_qy_rw_addr), + + .qy_wren (core_bram_qy_rw_wren), + + .k_din (core_bram_k_ro_dout), + .qy_dout (core_bram_qy_rw_din) + ); + + + // + // Output Selector + // + reg [0:0] bus_addr_upper_dly; + always @(posedge clk) bus_addr_upper_dly <= bus_addr_upper; + + reg [31: 0] bus_data_rd_mux; + assign bus_data_rd = bus_data_rd_mux; + + always @(*) + // + case (bus_addr_upper_dly) + // + BUS_ADDR_BANK_K: bus_data_rd_mux = user_bram_k_rw_dout; + BUS_ADDR_BANK_QY: bus_data_rd_mux = user_bram_qy_ro_dout; + // + endcase + + +endmodule diff --git a/rtl/ed25519_microcode.v b/rtl/ed25519_microcode.v deleted file mode 100644 index ec36e3f..0000000 --- a/rtl/ed25519_microcode.v +++ /dev/null @@ -1,426 +0,0 @@ -//====================================================================== -// -// Copyright (c) 2018, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module ed25519_microcode -( - input wire clk, - input wire [UOP_ADDR_WIDTH-1:0] addr, - output reg [UOP_DATA_WIDTH-1:0] data -); - -`include "ed25519_uop.v" - - always @(posedge clk) - // - case (addr) - - // PREPARE - 9'd000: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; - 9'd001: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; - 9'd002: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; - 9'd003: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T}; - 9'd004: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X}; - 9'd005: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y}; - 9'd006: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z}; - 9'd007: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T}; - 9'd008: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // BEFORE_ROUND_K0 - 9'd009: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; - 9'd010: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; - 9'd011: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; - 9'd012: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; - 9'd013: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; - 9'd014: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; - 9'd015: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; - 9'd016: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; - 9'd017: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // BEFORE_ROUND_K1 - 9'd018: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; - 9'd019: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; - 9'd020: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; - 9'd021: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; - 9'd022: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; - 9'd023: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; - 9'd024: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; - 9'd025: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; - 9'd026: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // DURING_ROUND - 9'd027: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_PROC_A}; - 9'd028: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_PROC_B}; - 9'd029: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_Z, UOP_OPERAND_CYCLE_U_Z, UOP_OPERAND_PROC_I}; - 9'd030: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_C}; - 9'd031: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_PROC_I}; - 9'd032: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_D}; - 9'd033: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_H}; - 9'd034: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_H, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_E}; - 9'd035: data <= {UOP_OPCODE_SUB, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_G}; - 9'd036: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_F}; - 9'd037: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_G, UOP_OPERAND_DONTCARE, UOP_OPERAND_PROC_G}; - 9'd038: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_H, UOP_OPERAND_DONTCARE, UOP_OPERAND_PROC_H}; - 9'd039: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_F, UOP_OPERAND_CYCLE_S_X}; - 9'd040: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_S_Y}; - 9'd041: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_S_T}; - 9'd042: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_F, UOP_OPERAND_PROC_G, UOP_OPERAND_CYCLE_S_Z}; - 9'd043: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Y, UOP_OPERAND_CYCLE_S_X, UOP_OPERAND_PROC_I}; - 9'd044: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_V_Y, UOP_OPERAND_CYCLE_V_X, UOP_OPERAND_PROC_J}; - 9'd045: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_J, UOP_OPERAND_PROC_A}; - 9'd046: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Y, UOP_OPERAND_CYCLE_S_X, UOP_OPERAND_PROC_I}; - 9'd047: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_V_Y, UOP_OPERAND_CYCLE_V_X, UOP_OPERAND_PROC_J}; - 9'd048: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_J, UOP_OPERAND_PROC_B}; - 9'd049: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Z, UOP_OPERAND_CYCLE_V_T, UOP_OPERAND_PROC_I}; - 9'd050: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_C}; - 9'd051: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_T, UOP_OPERAND_CYCLE_V_Z, UOP_OPERAND_PROC_I}; - 9'd052: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_D}; - 9'd053: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_E}; - 9'd054: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_F}; - 9'd055: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_G}; - 9'd056: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_H}; - 9'd057: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_F, UOP_OPERAND_CYCLE_T_X}; - 9'd058: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_T_Y}; - 9'd059: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_T_T}; - 9'd060: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_F, UOP_OPERAND_PROC_G, UOP_OPERAND_CYCLE_T_Z}; - 9'd061: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // AFTER_ROUND_K0 - 9'd062: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X}; - 9'd063: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y}; - 9'd064: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z}; - 9'd065: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T}; - 9'd066: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // AFTER_ROUND_K1 - 9'd067: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; - 9'd068: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; - 9'd069: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; - 9'd070: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T}; - 9'd071: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // BEFORE_INVERSION - 9'd072: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; - 9'd073: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1}; - 9'd074: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // DURING_INVERSION - 9'd075: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1}; - 9'd076: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_10}; - 9'd077: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_R1}; - 9'd078: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd079: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_1001}; - 9'd080: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_10}; - 9'd081: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1001, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_T_1011}; - 9'd082: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_R1}; - 9'd083: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_1001, UOP_OPERAND_INVERT_T_X5}; - 9'd084: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_X5, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd085: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd086: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd087: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd088: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd089: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd090: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_X5, UOP_OPERAND_INVERT_T_X10}; - 9'd091: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd092: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X10}; - 9'd093: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd094: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd095: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd096: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd097: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd098: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd099: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd100: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd101: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd102: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd103: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_INVERT_T_X20}; - 9'd104: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd105: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X20}; - 9'd106: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd107: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd108: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd109: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd110: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd111: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd112: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd113: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd114: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd115: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd116: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd117: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd118: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd119: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd120: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd121: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd122: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd123: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd124: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd125: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd126: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_INVERT_T_X40}; - 9'd127: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X40, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd128: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd129: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd130: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd131: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd132: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd133: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd134: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd135: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd136: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd137: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd138: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_INVERT_T_X50}; - 9'd139: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd140: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X50}; - 9'd141: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd142: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd143: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd144: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd145: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd146: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd147: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd148: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd149: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd150: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd151: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd152: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd153: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd154: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd155: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd156: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd157: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd158: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd159: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd160: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd161: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd162: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd163: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd164: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd165: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd166: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd167: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd168: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd169: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd170: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd171: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd172: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd173: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd174: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd175: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd176: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd177: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd178: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd179: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd180: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd181: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd182: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd183: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd184: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd185: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd186: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd187: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd188: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd189: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd190: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd191: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_INVERT_T_X100}; - 9'd192: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd193: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X100}; - 9'd194: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd195: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd196: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd197: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd198: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd199: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd200: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd201: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd202: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd203: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd204: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd205: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd206: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd207: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd208: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd209: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd210: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd211: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd212: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd213: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd214: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd215: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd216: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd217: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd218: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd219: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd220: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd221: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd222: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd223: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd224: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd225: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd226: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd227: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd228: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd229: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd230: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd231: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd232: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd233: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd234: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd235: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd236: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd237: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd238: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd239: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd240: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd241: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd242: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd243: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd244: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd245: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd246: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd247: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd248: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd249: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd250: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd251: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd252: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd253: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd254: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd255: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd256: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd257: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd258: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd259: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd260: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd261: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd262: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd263: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd264: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd265: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd266: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd267: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd268: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd269: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd270: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd271: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd272: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd273: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd274: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd275: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd276: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd277: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd278: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd279: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd280: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd281: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd282: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd283: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd284: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd285: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd286: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd287: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd288: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd289: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd290: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd291: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd292: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd293: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd294: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_INVERT_R2}; - 9'd295: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd296: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd297: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd298: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd299: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd300: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd301: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd302: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd303: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd304: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd305: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd306: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd307: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd308: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd309: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd310: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd311: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd312: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd313: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd314: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd315: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd316: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd317: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd318: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd319: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd320: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd321: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd322: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd323: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd324: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd325: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd326: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd327: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd328: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd329: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd330: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd331: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd332: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd333: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd334: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd335: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd336: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd337: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd338: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd339: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd340: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd341: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd342: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd343: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd344: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd345: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_INVERT_R1}; - 9'd346: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd347: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd348: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd349: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; - 9'd350: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; - 9'd351: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1011}; - 9'd352: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_R1}; - 9'd353: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // AFTER_INVERSION - 9'd354: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; - 9'd355: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_CYCLE_R0_X}; - 9'd356: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_CYCLE_R0_Y}; - 9'd357: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // FINAL_REDUCTION - 9'd358: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_CYCLE_R0_X}; - 9'd359: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_CYCLE_R0_Y}; - 9'd360: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // HANDLE_SIGN - 9'd361: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; - 9'd362: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - // OUTPUT - 9'd363: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; - 9'd364: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; - - endcase - -endmodule diff --git a/rtl/ed25519_microcode_rom.v b/rtl/ed25519_microcode_rom.v new file mode 100644 index 0000000..acce4fd --- /dev/null +++ b/rtl/ed25519_microcode_rom.v @@ -0,0 +1,426 @@ +//====================================================================== +// +// Copyright (c) 2018, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module ed25519_microcode_rom +( + input wire clk, + input wire [UOP_ADDR_WIDTH-1:0] addr, + output reg [UOP_DATA_WIDTH-1:0] data +); + +`include "ed25519_uop.vh" + + always @(posedge clk) + // + case (addr) + + // PREPARE + 9'd000: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; + 9'd001: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; + 9'd002: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; + 9'd003: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T}; + 9'd004: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X}; + 9'd005: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y}; + 9'd006: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z}; + 9'd007: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T}; + 9'd008: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // BEFORE_ROUND_K0 + 9'd009: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; + 9'd010: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; + 9'd011: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; + 9'd012: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; + 9'd013: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; + 9'd014: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; + 9'd015: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; + 9'd016: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; + 9'd017: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // BEFORE_ROUND_K1 + 9'd018: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; + 9'd019: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; + 9'd020: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; + 9'd021: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; + 9'd022: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; + 9'd023: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; + 9'd024: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; + 9'd025: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; + 9'd026: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // DURING_ROUND + 9'd027: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_PROC_A}; + 9'd028: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_PROC_B}; + 9'd029: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_Z, UOP_OPERAND_CYCLE_U_Z, UOP_OPERAND_PROC_I}; + 9'd030: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_C}; + 9'd031: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_U_X, UOP_OPERAND_CYCLE_U_Y, UOP_OPERAND_PROC_I}; + 9'd032: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_D}; + 9'd033: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_H}; + 9'd034: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_H, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_E}; + 9'd035: data <= {UOP_OPCODE_SUB, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_G}; + 9'd036: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_F}; + 9'd037: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_G, UOP_OPERAND_DONTCARE, UOP_OPERAND_PROC_G}; + 9'd038: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_H, UOP_OPERAND_DONTCARE, UOP_OPERAND_PROC_H}; + 9'd039: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_F, UOP_OPERAND_CYCLE_S_X}; + 9'd040: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_S_Y}; + 9'd041: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_S_T}; + 9'd042: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_F, UOP_OPERAND_PROC_G, UOP_OPERAND_CYCLE_S_Z}; + 9'd043: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Y, UOP_OPERAND_CYCLE_S_X, UOP_OPERAND_PROC_I}; + 9'd044: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_V_Y, UOP_OPERAND_CYCLE_V_X, UOP_OPERAND_PROC_J}; + 9'd045: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_J, UOP_OPERAND_PROC_A}; + 9'd046: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Y, UOP_OPERAND_CYCLE_S_X, UOP_OPERAND_PROC_I}; + 9'd047: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_V_Y, UOP_OPERAND_CYCLE_V_X, UOP_OPERAND_PROC_J}; + 9'd048: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_J, UOP_OPERAND_PROC_B}; + 9'd049: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_Z, UOP_OPERAND_CYCLE_V_T, UOP_OPERAND_PROC_I}; + 9'd050: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_C}; + 9'd051: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_S_T, UOP_OPERAND_CYCLE_V_Z, UOP_OPERAND_PROC_I}; + 9'd052: data <= {UOP_OPCODE_ADD, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_I, UOP_OPERAND_PROC_D}; + 9'd053: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_E}; + 9'd054: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_F}; + 9'd055: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_B, UOP_OPERAND_PROC_A, UOP_OPERAND_PROC_G}; + 9'd056: data <= {UOP_OPCODE_SUB, UOP_BANKS_HI2LO, UOP_OPERAND_PROC_D, UOP_OPERAND_PROC_C, UOP_OPERAND_PROC_H}; + 9'd057: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_F, UOP_OPERAND_CYCLE_T_X}; + 9'd058: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_G, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_T_Y}; + 9'd059: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_E, UOP_OPERAND_PROC_H, UOP_OPERAND_CYCLE_T_T}; + 9'd060: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_PROC_F, UOP_OPERAND_PROC_G, UOP_OPERAND_CYCLE_T_Z}; + 9'd061: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // AFTER_ROUND_K0 + 9'd062: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X}; + 9'd063: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y}; + 9'd064: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z}; + 9'd065: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T}; + 9'd066: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // AFTER_ROUND_K1 + 9'd067: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; + 9'd068: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; + 9'd069: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; + 9'd070: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_T_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T}; + 9'd071: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // BEFORE_INVERSION + 9'd072: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; + 9'd073: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1}; + 9'd074: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // DURING_INVERSION + 9'd075: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1}; + 9'd076: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_10}; + 9'd077: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_R1}; + 9'd078: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd079: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_1, UOP_OPERAND_INVERT_T_1001}; + 9'd080: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_10}; + 9'd081: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_1001, UOP_OPERAND_INVERT_T_10, UOP_OPERAND_INVERT_T_1011}; + 9'd082: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_R1}; + 9'd083: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_1001, UOP_OPERAND_INVERT_T_X5}; + 9'd084: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_X5, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd085: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd086: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd087: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd088: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd089: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd090: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_X5, UOP_OPERAND_INVERT_T_X10}; + 9'd091: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd092: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X10}; + 9'd093: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd094: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd095: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd096: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd097: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd098: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd099: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd100: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd101: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd102: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd103: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_INVERT_T_X20}; + 9'd104: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd105: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X20}; + 9'd106: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd107: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd108: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd109: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd110: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd111: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd112: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd113: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd114: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd115: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd116: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd117: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd118: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd119: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd120: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd121: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd122: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd123: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd124: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd125: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd126: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X20, UOP_OPERAND_INVERT_T_X40}; + 9'd127: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X40, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd128: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd129: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd130: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd131: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd132: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd133: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd134: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd135: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd136: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd137: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd138: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X10, UOP_OPERAND_INVERT_T_X50}; + 9'd139: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd140: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X50}; + 9'd141: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd142: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd143: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd144: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd145: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd146: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd147: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd148: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd149: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd150: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd151: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd152: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd153: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd154: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd155: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd156: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd157: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd158: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd159: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd160: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd161: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd162: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd163: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd164: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd165: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd166: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd167: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd168: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd169: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd170: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd171: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd172: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd173: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd174: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd175: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd176: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd177: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd178: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd179: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd180: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd181: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd182: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd183: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd184: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd185: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd186: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd187: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd188: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd189: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd190: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd191: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_INVERT_T_X100}; + 9'd192: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd193: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_X100}; + 9'd194: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd195: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd196: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd197: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd198: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd199: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd200: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd201: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd202: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd203: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd204: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd205: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd206: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd207: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd208: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd209: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd210: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd211: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd212: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd213: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd214: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd215: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd216: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd217: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd218: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd219: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd220: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd221: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd222: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd223: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd224: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd225: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd226: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd227: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd228: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd229: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd230: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd231: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd232: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd233: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd234: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd235: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd236: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd237: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd238: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd239: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd240: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd241: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd242: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd243: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd244: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd245: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd246: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd247: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd248: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd249: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd250: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd251: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd252: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd253: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd254: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd255: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd256: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd257: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd258: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd259: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd260: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd261: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd262: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd263: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd264: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd265: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd266: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd267: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd268: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd269: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd270: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd271: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd272: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd273: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd274: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd275: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd276: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd277: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd278: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd279: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd280: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd281: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd282: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd283: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd284: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd285: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd286: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd287: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd288: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd289: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd290: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd291: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd292: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd293: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd294: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_T_X100, UOP_OPERAND_INVERT_R2}; + 9'd295: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd296: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd297: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd298: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd299: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd300: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd301: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd302: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd303: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd304: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd305: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd306: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd307: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd308: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd309: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd310: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd311: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd312: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd313: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd314: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd315: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd316: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd317: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd318: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd319: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd320: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd321: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd322: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd323: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd324: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd325: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd326: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd327: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd328: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd329: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd330: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd331: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd332: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd333: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd334: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd335: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd336: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd337: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd338: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd339: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd340: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd341: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd342: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd343: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd344: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd345: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_X50, UOP_OPERAND_INVERT_R1}; + 9'd346: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd347: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd348: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd349: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_R1}; + 9'd350: data <= {UOP_OPCODE_MUL, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R1, UOP_OPERAND_INVERT_R2}; + 9'd351: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_T_1011}; + 9'd352: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R2, UOP_OPERAND_INVERT_T_1011, UOP_OPERAND_INVERT_R1}; + 9'd353: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // AFTER_INVERSION + 9'd354: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_INVERT_R1, UOP_OPERAND_DONTCARE, UOP_OPERAND_INVERT_R1}; + 9'd355: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_CYCLE_R0_X}; + 9'd356: data <= {UOP_OPCODE_MUL, UOP_BANKS_LO2HI, UOP_OPERAND_INVERT_R1, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_CYCLE_R0_Y}; + 9'd357: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // FINAL_REDUCTION + 9'd358: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_CYCLE_R0_X}; + 9'd359: data <= {UOP_OPCODE_ADD, UOP_BANKS_HI2LO, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_CYCLE_R0_Y}; + 9'd360: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // HANDLE_SIGN + 9'd361: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; + 9'd362: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + // OUTPUT + 9'd363: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; + 9'd364: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + + endcase + +endmodule diff --git a/rtl/ed25519_multiplier.v b/rtl/ed25519_multiplier.v deleted file mode 100644 index 31a4b18..0000000 --- a/rtl/ed25519_multiplier.v +++ /dev/null @@ -1,329 +0,0 @@ -//------------------------------------------------------------------------------ -// -// ed25519_multiplier.v -// ----------------------------------------------------------------------------- -// Ed25519 base point scalar multiplier. -// -// Authors: Pavel Shatov -// -// Copyright (c) 2018, NORDUnet A/S -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//------------------------------------------------------------------------------ - -module ed25519_multiplier -( - clk, rst_n, - ena, rdy, - k_addr, qy_addr, - qy_wren, - k_din, - qy_dout -); - - - // - // Microcode Header - // -`include "ed25519_uop.v" - - - // - // Ports - // - input clk; // system clock - input rst_n; // active-low async reset - - input ena; // enable input - output rdy; // ready output - - output [ 2:0] k_addr; // - output [ 2:0] qy_addr; // - output qy_wren; // - input [31:0] k_din; // - output [31:0] qy_dout; // - - - // - // FSM - // - localparam [4:0] FSM_STATE_IDLE = 5'd00; - localparam [4:0] FSM_STATE_PREPARE_TRIG = 5'd01; - localparam [4:0] FSM_STATE_PREPARE_WAIT = 5'd02; - localparam [4:0] FSM_STATE_BEFORE_ROUND_TRIG = 5'd03; - localparam [4:0] FSM_STATE_BEFORE_ROUND_WAIT = 5'd04; - localparam [4:0] FSM_STATE_DURING_ROUND_TRIG = 5'd05; - localparam [4:0] FSM_STATE_DURING_ROUND_WAIT = 5'd06; - localparam [4:0] FSM_STATE_AFTER_ROUND_TRIG = 5'd07; - localparam [4:0] FSM_STATE_AFTER_ROUND_WAIT = 5'd08; - localparam [4:0] FSM_STATE_BEFORE_INVERT_TRIG = 5'd09; - localparam [4:0] FSM_STATE_BEFORE_INVERT_WAIT = 5'd10; - localparam [4:0] FSM_STATE_DURING_INVERT_TRIG = 5'd11; - localparam [4:0] FSM_STATE_DURING_INVERT_WAIT = 5'd12; - localparam [4:0] FSM_STATE_AFTER_INVERT_TRIG = 5'd13; - localparam [4:0] FSM_STATE_AFTER_INVERT_WAIT = 5'd14; - localparam [4:0] FSM_STATE_FINAL_REDUCE_TRIG = 5'd15; - localparam [4:0] FSM_STATE_FINAL_REDUCE_WAIT = 5'd16; - localparam [4:0] FSM_STATE_HANDLE_SIGN_TRIG = 5'd17; - localparam [4:0] FSM_STATE_HANDLE_SIGN_WAIT = 5'd18; - localparam [4:0] FSM_STATE_OUTPUT_TRIG = 5'd19; - localparam [4:0] FSM_STATE_OUTPUT_WAIT = 5'd20; - localparam [4:0] FSM_STATE_DONE = 5'd31; - - reg [4:0] fsm_state = FSM_STATE_IDLE; - reg [4:0] fsm_state_next; - - - // - // Round Counter - // - reg [7:0] bit_counter; - wire [7:0] bit_counter_max = 8'hFF; // 255 - wire [7:0] bit_counter_zero = 8'h00; // 0 - wire [7:0] bit_counter_next = - (bit_counter < bit_counter_max) ? bit_counter + 1'b1 : bit_counter_zero; - - assign k_addr = bit_counter[7:5]; - - - // - // Worker Trigger Logic - // - reg worker_trig = 1'b0; - wire worker_done; - - wire fsm_wait_done = !worker_trig && worker_done; - - always @(posedge clk or negedge rst_n) - // - if (rst_n == 1'b0) worker_trig <= 1'b0; - else case (fsm_state) - FSM_STATE_PREPARE_TRIG, - FSM_STATE_BEFORE_ROUND_TRIG, - FSM_STATE_DURING_ROUND_TRIG, - FSM_STATE_AFTER_ROUND_TRIG, - FSM_STATE_BEFORE_INVERT_TRIG, - FSM_STATE_DURING_INVERT_TRIG, - FSM_STATE_AFTER_INVERT_TRIG, - FSM_STATE_FINAL_REDUCE_TRIG, - FSM_STATE_HANDLE_SIGN_TRIG, - FSM_STATE_OUTPUT_TRIG: worker_trig <= 1'b1; - default: worker_trig <= 1'b0; - endcase - - - // - // Round Counter Increment Logic - // - always @(posedge clk) - // - case (fsm_state_next) - FSM_STATE_PREPARE_TRIG: bit_counter <= bit_counter_zero; - FSM_STATE_AFTER_ROUND_TRIG: bit_counter <= bit_counter_next; - endcase - - - // - // Final Round Detection Logic - // - wire [ 3: 0] fsm_state_after_round = (bit_counter != bit_counter_zero) ? - FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_BEFORE_INVERT_TRIG; - - - // - // K Latch - // - reg [31:0] k_din_shreg; - - wire [4:0] k_bit_index = bit_counter[4:0]; - - always @(posedge clk) - // - if (fsm_state_next == FSM_STATE_BEFORE_ROUND_TRIG) - // - if (k_bit_index == 5'd0) - // - case (k_addr) - 3'd0: k_din_shreg <= {k_din[31:3], 3'b000}; - 3'd7: k_din_shreg <= {2'b01, k_din[29:0]}; - default: k_din_shreg <= k_din; - endcase - // - else k_din_shreg <= {k_din_shreg[0], k_din_shreg[31:1]}; - - - // - // Worker Offset Logic - // - reg [UOP_ADDR_WIDTH-1:0] worker_offset; - - always @(posedge clk) - // - case (fsm_state) - FSM_STATE_PREPARE_TRIG: worker_offset <= UOP_OFFSET_PREPARE; - FSM_STATE_BEFORE_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_BEFORE_ROUND_K1 : UOP_OFFSET_BEFORE_ROUND_K0; - FSM_STATE_DURING_ROUND_TRIG: worker_offset <= UOP_OFFSET_DURING_ROUND; - FSM_STATE_AFTER_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_AFTER_ROUND_K1 : UOP_OFFSET_AFTER_ROUND_K0; - FSM_STATE_BEFORE_INVERT_TRIG: worker_offset <= UOP_OFFSET_BEFORE_INVERSION; - FSM_STATE_DURING_INVERT_TRIG: worker_offset <= UOP_OFFSET_DURING_INVERSION; - FSM_STATE_AFTER_INVERT_TRIG: worker_offset <= UOP_OFFSET_AFTER_INVERSION; - FSM_STATE_FINAL_REDUCE_TRIG: worker_offset <= UOP_OFFSET_FINAL_REDUCTION; - FSM_STATE_HANDLE_SIGN_TRIG: worker_offset <= UOP_OFFSET_HANDLE_SIGN; - FSM_STATE_OUTPUT_TRIG: worker_offset <= UOP_OFFSET_OUTPUT; - default: worker_offset <= {UOP_ADDR_WIDTH{1'bX}}; - endcase - - - // - // FSM Process - // - always @(posedge clk or negedge rst_n) - // - if (rst_n == 1'b0) fsm_state <= FSM_STATE_IDLE; - else fsm_state <= fsm_state_next; - - - // - // FSM Transition Logic - // - always @* begin - // - fsm_state_next = FSM_STATE_IDLE; - // - case (fsm_state) - - FSM_STATE_IDLE: fsm_state_next = ena ? FSM_STATE_PREPARE_TRIG : FSM_STATE_IDLE; - - FSM_STATE_PREPARE_TRIG: fsm_state_next = FSM_STATE_PREPARE_WAIT; - FSM_STATE_PREPARE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_PREPARE_WAIT; - - FSM_STATE_BEFORE_ROUND_TRIG: fsm_state_next = FSM_STATE_BEFORE_ROUND_WAIT; - FSM_STATE_BEFORE_ROUND_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DURING_ROUND_TRIG : FSM_STATE_BEFORE_ROUND_WAIT; - - FSM_STATE_DURING_ROUND_TRIG: fsm_state_next = FSM_STATE_DURING_ROUND_WAIT; - FSM_STATE_DURING_ROUND_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_ROUND_TRIG : FSM_STATE_DURING_ROUND_WAIT; - - FSM_STATE_AFTER_ROUND_TRIG: fsm_state_next = FSM_STATE_AFTER_ROUND_WAIT; - FSM_STATE_AFTER_ROUND_WAIT: fsm_state_next = fsm_wait_done ? fsm_state_after_round : FSM_STATE_AFTER_ROUND_WAIT; - - FSM_STATE_BEFORE_INVERT_TRIG: fsm_state_next = FSM_STATE_BEFORE_INVERT_WAIT; - FSM_STATE_BEFORE_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DURING_INVERT_TRIG : FSM_STATE_BEFORE_INVERT_WAIT; - - FSM_STATE_DURING_INVERT_TRIG: fsm_state_next = FSM_STATE_DURING_INVERT_WAIT; - FSM_STATE_DURING_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_INVERT_TRIG : FSM_STATE_DURING_INVERT_WAIT; - - FSM_STATE_AFTER_INVERT_TRIG: fsm_state_next = FSM_STATE_AFTER_INVERT_WAIT; - FSM_STATE_AFTER_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_FINAL_REDUCE_TRIG : FSM_STATE_AFTER_INVERT_WAIT; - - FSM_STATE_FINAL_REDUCE_TRIG: fsm_state_next = FSM_STATE_FINAL_REDUCE_WAIT; - FSM_STATE_FINAL_REDUCE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_HANDLE_SIGN_TRIG : FSM_STATE_FINAL_REDUCE_WAIT; - - FSM_STATE_HANDLE_SIGN_TRIG: fsm_state_next = FSM_STATE_HANDLE_SIGN_WAIT; - FSM_STATE_HANDLE_SIGN_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_OUTPUT_TRIG : FSM_STATE_HANDLE_SIGN_WAIT; - - FSM_STATE_OUTPUT_TRIG: fsm_state_next = FSM_STATE_OUTPUT_WAIT; - FSM_STATE_OUTPUT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DONE : FSM_STATE_OUTPUT_WAIT; - - FSM_STATE_DONE: fsm_state_next = FSM_STATE_IDLE; - - endcase - // - end - - - // - // Debug - // - wire debug_dump_now = fsm_state == FSM_STATE_OUTPUT_TRIG; - - reg [6:0] debug_dump_addr1 = {1'bX, UOP_OPERAND_INVERT_R1}; - reg [6:0] debug_dump_addr2 = {1'b0, UOP_OPERAND_CYCLE_R0_X}; - reg [6:0] debug_dump_addr3 = {1'b0, UOP_OPERAND_CYCLE_R0_Y}; - reg [6:0] debug_dump_addr4 = {1'bX, UOP_OPERAND_CYCLE_R0_T}; - reg [6:0] debug_dump_addr5 = {1'bX, UOP_OPERAND_CYCLE_R1_X}; - reg [6:0] debug_dump_addr6 = {1'bX, UOP_OPERAND_CYCLE_R1_Y}; - reg [6:0] debug_dump_addr7 = {1'bX, UOP_OPERAND_CYCLE_R1_Z}; - reg [6:0] debug_dump_addr8 = {1'bX, UOP_OPERAND_CYCLE_R1_T}; - - // - // Worker - // - - wire worker_final_reduce = fsm_state == FSM_STATE_FINAL_REDUCE_WAIT; - wire worker_handle_sign = fsm_state == FSM_STATE_HANDLE_SIGN_WAIT; - wire worker_output_now = fsm_state == FSM_STATE_OUTPUT_WAIT; - - ed25519_worker uop_worker - ( - .clk (clk), - .rst_n (rst_n), - .debug_dump_now (debug_dump_now), - - .debug_dump_addr1 (debug_dump_addr1), - .debug_dump_addr2 (debug_dump_addr2), - .debug_dump_addr3 (debug_dump_addr3), - .debug_dump_addr4 (debug_dump_addr4), - .debug_dump_addr5 (debug_dump_addr5), - .debug_dump_addr6 (debug_dump_addr6), - .debug_dump_addr7 (debug_dump_addr7), - .debug_dump_addr8 (debug_dump_addr8), - - .ena (worker_trig), - .rdy (worker_done), - .uop_offset (worker_offset), - .final_reduce (worker_final_reduce), - .handle_sign (worker_handle_sign), - .output_now (worker_output_now), - - .y_addr (qy_addr), - .y_dout (qy_dout), - .y_wren (qy_wren) - ); - - - // - // Ready Flag Logic - // - reg rdy_reg = 1'b1; - assign rdy = rdy_reg; - - always @(posedge clk or negedge rst_n) - // - if (rst_n == 1'b0) rdy_reg <= 1'b1; - else case (fsm_state) - FSM_STATE_IDLE: if (ena) rdy_reg <= 1'b0; - FSM_STATE_DONE: rdy_reg <= 1'b1; - endcase - - -endmodule - - -//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_operand_bank.v b/rtl/ed25519_operand_bank.v new file mode 100644 index 0000000..21ebbfc --- /dev/null +++ b/rtl/ed25519_operand_bank.v @@ -0,0 +1,140 @@ +//====================================================================== +// +// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +`timescale 1ns / 1ps + +module ed25519_operand_bank +( + input clk, + + input [ 9-1:0] a_addr, + input a_wr, + input [32-1:0] a_in, + + input [ 9-1:0] b_addr, + output [32-1:0] b_out +); + + + // + // BRAM + // + reg [31:0] bram[0:64*8-1]; + + + // + // Initialization + // + initial begin + // + // CONST_ZERO + // + bram[ 0*8 + 7] = 32'h00000000; + bram[ 0*8 + 6] = 32'h00000000; + bram[ 0*8 + 5] = 32'h00000000; + bram[ 0*8 + 4] = 32'h00000000; + bram[ 0*8 + 3] = 32'h00000000; + bram[ 0*8 + 2] = 32'h00000000; + bram[ 0*8 + 1] = 32'h00000000; + bram[ 0*8 + 0] = 32'h00000000; + // + // CONST_ONE + // + bram[ 1*8 + 7] = 32'h00000000; + bram[ 1*8 + 6] = 32'h00000000; + bram[ 1*8 + 5] = 32'h00000000; + bram[ 1*8 + 4] = 32'h00000000; + bram[ 1*8 + 3] = 32'h00000000; + bram[ 1*8 + 2] = 32'h00000000; + bram[ 1*8 + 1] = 32'h00000000; + bram[ 1*8 + 0] = 32'h00000001; + // + // G_X + // + bram[14*8 + 7] = 32'h216936d3; + bram[14*8 + 6] = 32'hcd6e53fe; + bram[14*8 + 5] = 32'hc0a4e231; + bram[14*8 + 4] = 32'hfdd6dc5c; + bram[14*8 + 3] = 32'h692cc760; + bram[14*8 + 2] = 32'h9525a7b2; + bram[14*8 + 1] = 32'hc9562d60; + bram[14*8 + 0] = 32'h8f25d51a; + // + // G_Y + // + bram[15*8 + 7] = 32'h66666666; + bram[15*8 + 6] = 32'h66666666; + bram[15*8 + 5] = 32'h66666666; + bram[15*8 + 4] = 32'h66666666; + bram[15*8 + 3] = 32'h66666666; + bram[15*8 + 2] = 32'h66666666; + bram[15*8 + 1] = 32'h66666666; + bram[15*8 + 0] = 32'h66666658; + // + // G_T + // + bram[16*8 + 7] = 32'h67875f0f; + bram[16*8 + 6] = 32'hd78b7665; + bram[16*8 + 5] = 32'h66ea4e8e; + bram[16*8 + 4] = 32'h64abe37d; + bram[16*8 + 3] = 32'h20f09f80; + bram[16*8 + 2] = 32'h775152f5; + bram[16*8 + 1] = 32'h6dde8ab3; + bram[16*8 + 0] = 32'ha5b7dda3; + end + + + // + // Output Register + // + reg [32-1:0] bram_reg_b; + + assign b_out = bram_reg_b; + + + // + // Write Port A + // + always @(posedge clk) + // + if (a_wr) bram[a_addr] <= a_in; + + + // + // Read Port B + // + always @(posedge clk) + // + bram_reg_b <= bram[b_addr]; + + +endmodule diff --git a/rtl/ed25519_uop.v b/rtl/ed25519_uop.v deleted file mode 100644 index 12b9e10..0000000 --- a/rtl/ed25519_uop.v +++ /dev/null @@ -1,128 +0,0 @@ -//====================================================================== -// -// Copyright (c) 2018, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -localparam integer UOP_ADDR_WIDTH = 9; // 2 ^ 9 = max 512 instructions - -localparam integer UOP_DATA_WIDTH = 5 + 1 + 3 * 6; // opcode + banks + 3 * operand (2 * src + dst) - -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_PREPARE = 9'd000; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_ROUND_K0 = 9'd009; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_ROUND_K1 = 9'd018; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_DURING_ROUND = 9'd027; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_ROUND_K0 = 9'd062; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_ROUND_K1 = 9'd067; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_INVERSION = 9'd072; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_DURING_INVERSION = 9'd075; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_INVERSION = 9'd354; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_FINAL_REDUCTION = 9'd358; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_HANDLE_SIGN = 9'd361; -localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_OUTPUT = 9'd363; - -localparam [4:0] UOP_OPCODE_COPY = 5'b00001; -localparam [4:0] UOP_OPCODE_ADD = 5'b00010; -localparam [4:0] UOP_OPCODE_SUB = 5'b00100; -localparam [4:0] UOP_OPCODE_MUL = 5'b01000; -localparam [4:0] UOP_OPCODE_STOP = 5'b10000; - -localparam UOP_BANKS_LO2HI = 1'b0; -localparam UOP_BANKS_HI2LO = 1'b1; -localparam UOP_BANKS_DUMMY = 1'bX; - -localparam [5:0] UOP_OPERAND_CONST_ZERO = 6'd00; -localparam [5:0] UOP_OPERAND_CONST_ONE = 6'd01; - -localparam [5:0] UOP_OPERAND_INVERT_R1 = 6'd02; -localparam [5:0] UOP_OPERAND_INVERT_R2 = 6'd03; - -localparam [5:0] UOP_OPERAND_INVERT_T_1 = 6'd04; -localparam [5:0] UOP_OPERAND_INVERT_T_10 = 6'd05; -localparam [5:0] UOP_OPERAND_INVERT_T_1001 = 6'd06; -localparam [5:0] UOP_OPERAND_INVERT_T_1011 = 6'd07; - -localparam [5:0] UOP_OPERAND_INVERT_T_X5 = 6'd08; -localparam [5:0] UOP_OPERAND_INVERT_T_X10 = 6'd09; -localparam [5:0] UOP_OPERAND_INVERT_T_X20 = 6'd10; -localparam [5:0] UOP_OPERAND_INVERT_T_X40 = 6'd11; -localparam [5:0] UOP_OPERAND_INVERT_T_X50 = 6'd12; -localparam [5:0] UOP_OPERAND_INVERT_T_X100 = 6'd13; - -localparam [5:0] UOP_OPERAND_CONST_G_X = 6'd14; -localparam [5:0] UOP_OPERAND_CONST_G_Y = 6'd15; -localparam [5:0] UOP_OPERAND_CONST_G_T = 6'd16; - -localparam [5:0] UOP_OPERAND_CYCLE_R0_X = 6'd17; -localparam [5:0] UOP_OPERAND_CYCLE_R0_Y = 6'd18; -localparam [5:0] UOP_OPERAND_CYCLE_R0_Z = 6'd19; -localparam [5:0] UOP_OPERAND_CYCLE_R0_T = 6'd20; - -localparam [5:0] UOP_OPERAND_CYCLE_R1_X = 6'd21; -localparam [5:0] UOP_OPERAND_CYCLE_R1_Y = 6'd22; -localparam [5:0] UOP_OPERAND_CYCLE_R1_Z = 6'd23; -localparam [5:0] UOP_OPERAND_CYCLE_R1_T = 6'd24; - -localparam [5:0] UOP_OPERAND_CYCLE_S_X = 6'd25; -localparam [5:0] UOP_OPERAND_CYCLE_S_Y = 6'd26; -localparam [5:0] UOP_OPERAND_CYCLE_S_Z = 6'd27; -localparam [5:0] UOP_OPERAND_CYCLE_S_T = 6'd28; - -localparam [5:0] UOP_OPERAND_CYCLE_T_X = 6'd29; -localparam [5:0] UOP_OPERAND_CYCLE_T_Y = 6'd30; -localparam [5:0] UOP_OPERAND_CYCLE_T_Z = 6'd31; -localparam [5:0] UOP_OPERAND_CYCLE_T_T = 6'd32; - -localparam [5:0] UOP_OPERAND_CYCLE_U_X = 6'd33; -localparam [5:0] UOP_OPERAND_CYCLE_U_Y = 6'd34; -localparam [5:0] UOP_OPERAND_CYCLE_U_Z = 6'd35; -localparam [5:0] UOP_OPERAND_CYCLE_U_T = 6'd36; - -localparam [5:0] UOP_OPERAND_CYCLE_V_X = 6'd37; -localparam [5:0] UOP_OPERAND_CYCLE_V_Y = 6'd38; -localparam [5:0] UOP_OPERAND_CYCLE_V_Z = 6'd39; -localparam [5:0] UOP_OPERAND_CYCLE_V_T = 6'd40; - -localparam [5:0] UOP_OPERAND_PROC_A = 6'd41; -localparam [5:0] UOP_OPERAND_PROC_B = 6'd42; -localparam [5:0] UOP_OPERAND_PROC_C = 6'd43; -localparam [5:0] UOP_OPERAND_PROC_D = 6'd44; -localparam [5:0] UOP_OPERAND_PROC_E = 6'd45; -localparam [5:0] UOP_OPERAND_PROC_F = 6'd46; -localparam [5:0] UOP_OPERAND_PROC_G = 6'd47; -localparam [5:0] UOP_OPERAND_PROC_H = 6'd48; -localparam [5:0] UOP_OPERAND_PROC_I = 6'd49; -localparam [5:0] UOP_OPERAND_PROC_J = 6'd50; - -localparam [5:0] UOP_OPERAND_DONTCARE = 6'dXX; - - -//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_uop.vh b/rtl/ed25519_uop.vh new file mode 100644 index 0000000..12b9e10 --- /dev/null +++ b/rtl/ed25519_uop.vh @@ -0,0 +1,128 @@ +//====================================================================== +// +// Copyright (c) 2018, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +localparam integer UOP_ADDR_WIDTH = 9; // 2 ^ 9 = max 512 instructions + +localparam integer UOP_DATA_WIDTH = 5 + 1 + 3 * 6; // opcode + banks + 3 * operand (2 * src + dst) + +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_PREPARE = 9'd000; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_ROUND_K0 = 9'd009; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_ROUND_K1 = 9'd018; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_DURING_ROUND = 9'd027; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_ROUND_K0 = 9'd062; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_ROUND_K1 = 9'd067; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_BEFORE_INVERSION = 9'd072; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_DURING_INVERSION = 9'd075; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_AFTER_INVERSION = 9'd354; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_FINAL_REDUCTION = 9'd358; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_HANDLE_SIGN = 9'd361; +localparam [UOP_ADDR_WIDTH-1:0] UOP_OFFSET_OUTPUT = 9'd363; + +localparam [4:0] UOP_OPCODE_COPY = 5'b00001; +localparam [4:0] UOP_OPCODE_ADD = 5'b00010; +localparam [4:0] UOP_OPCODE_SUB = 5'b00100; +localparam [4:0] UOP_OPCODE_MUL = 5'b01000; +localparam [4:0] UOP_OPCODE_STOP = 5'b10000; + +localparam UOP_BANKS_LO2HI = 1'b0; +localparam UOP_BANKS_HI2LO = 1'b1; +localparam UOP_BANKS_DUMMY = 1'bX; + +localparam [5:0] UOP_OPERAND_CONST_ZERO = 6'd00; +localparam [5:0] UOP_OPERAND_CONST_ONE = 6'd01; + +localparam [5:0] UOP_OPERAND_INVERT_R1 = 6'd02; +localparam [5:0] UOP_OPERAND_INVERT_R2 = 6'd03; + +localparam [5:0] UOP_OPERAND_INVERT_T_1 = 6'd04; +localparam [5:0] UOP_OPERAND_INVERT_T_10 = 6'd05; +localparam [5:0] UOP_OPERAND_INVERT_T_1001 = 6'd06; +localparam [5:0] UOP_OPERAND_INVERT_T_1011 = 6'd07; + +localparam [5:0] UOP_OPERAND_INVERT_T_X5 = 6'd08; +localparam [5:0] UOP_OPERAND_INVERT_T_X10 = 6'd09; +localparam [5:0] UOP_OPERAND_INVERT_T_X20 = 6'd10; +localparam [5:0] UOP_OPERAND_INVERT_T_X40 = 6'd11; +localparam [5:0] UOP_OPERAND_INVERT_T_X50 = 6'd12; +localparam [5:0] UOP_OPERAND_INVERT_T_X100 = 6'd13; + +localparam [5:0] UOP_OPERAND_CONST_G_X = 6'd14; +localparam [5:0] UOP_OPERAND_CONST_G_Y = 6'd15; +localparam [5:0] UOP_OPERAND_CONST_G_T = 6'd16; + +localparam [5:0] UOP_OPERAND_CYCLE_R0_X = 6'd17; +localparam [5:0] UOP_OPERAND_CYCLE_R0_Y = 6'd18; +localparam [5:0] UOP_OPERAND_CYCLE_R0_Z = 6'd19; +localparam [5:0] UOP_OPERAND_CYCLE_R0_T = 6'd20; + +localparam [5:0] UOP_OPERAND_CYCLE_R1_X = 6'd21; +localparam [5:0] UOP_OPERAND_CYCLE_R1_Y = 6'd22; +localparam [5:0] UOP_OPERAND_CYCLE_R1_Z = 6'd23; +localparam [5:0] UOP_OPERAND_CYCLE_R1_T = 6'd24; + +localparam [5:0] UOP_OPERAND_CYCLE_S_X = 6'd25; +localparam [5:0] UOP_OPERAND_CYCLE_S_Y = 6'd26; +localparam [5:0] UOP_OPERAND_CYCLE_S_Z = 6'd27; +localparam [5:0] UOP_OPERAND_CYCLE_S_T = 6'd28; + +localparam [5:0] UOP_OPERAND_CYCLE_T_X = 6'd29; +localparam [5:0] UOP_OPERAND_CYCLE_T_Y = 6'd30; +localparam [5:0] UOP_OPERAND_CYCLE_T_Z = 6'd31; +localparam [5:0] UOP_OPERAND_CYCLE_T_T = 6'd32; + +localparam [5:0] UOP_OPERAND_CYCLE_U_X = 6'd33; +localparam [5:0] UOP_OPERAND_CYCLE_U_Y = 6'd34; +localparam [5:0] UOP_OPERAND_CYCLE_U_Z = 6'd35; +localparam [5:0] UOP_OPERAND_CYCLE_U_T = 6'd36; + +localparam [5:0] UOP_OPERAND_CYCLE_V_X = 6'd37; +localparam [5:0] UOP_OPERAND_CYCLE_V_Y = 6'd38; +localparam [5:0] UOP_OPERAND_CYCLE_V_Z = 6'd39; +localparam [5:0] UOP_OPERAND_CYCLE_V_T = 6'd40; + +localparam [5:0] UOP_OPERAND_PROC_A = 6'd41; +localparam [5:0] UOP_OPERAND_PROC_B = 6'd42; +localparam [5:0] UOP_OPERAND_PROC_C = 6'd43; +localparam [5:0] UOP_OPERAND_PROC_D = 6'd44; +localparam [5:0] UOP_OPERAND_PROC_E = 6'd45; +localparam [5:0] UOP_OPERAND_PROC_F = 6'd46; +localparam [5:0] UOP_OPERAND_PROC_G = 6'd47; +localparam [5:0] UOP_OPERAND_PROC_H = 6'd48; +localparam [5:0] UOP_OPERAND_PROC_I = 6'd49; +localparam [5:0] UOP_OPERAND_PROC_J = 6'd50; + +localparam [5:0] UOP_OPERAND_DONTCARE = 6'dXX; + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_uop_worker.v b/rtl/ed25519_uop_worker.v new file mode 100644 index 0000000..244ff97 --- /dev/null +++ b/rtl/ed25519_uop_worker.v @@ -0,0 +1,520 @@ +//------------------------------------------------------------------------------ +// +// ed25519_uop_worker.v +// ----------------------------------------------------------------------------- +// Ed25519 uOP Worker. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2018, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module ed25519_uop_worker +( + clk, rst_n, + ena, rdy, + uop_offset, + final_reduce, + handle_sign, + output_now, + y_addr, y_dout, y_wren +); + + + // + // Microcode Header + // +`include "ed25519_uop.vh" + + + // + // Ports + // + input clk; // system clock + input rst_n; // active-low async reset + + input ena; // enable input + output rdy; // ready output + + input [UOP_ADDR_WIDTH-1:0] uop_offset; // starting offset + + input final_reduce; // use regular (not double) modulus + input handle_sign; // handle sign of x + input output_now; // produce output + + output [ 2: 0] y_addr; + output [31: 0] y_dout; + output y_wren; + + + // + // Constants + // + localparam integer OPERAND_NUM_WORDS = 8; // 256 bits -> 8 x 32-bit words + localparam integer WORD_COUNTER_WIDTH = 3; // 0..7 -> 3 bits + + + // + // FSM + // + localparam [1:0] FSM_STATE_IDLE = 2'b00; + localparam [1:0] FSM_STATE_FETCH = 2'b01; + localparam [1:0] FSM_STATE_DECODE = 2'b10; + localparam [1:0] FSM_STATE_BUSY = 2'b11; + + reg [1:0] fsm_state = FSM_STATE_IDLE; + reg [1:0] fsm_state_next; + + + // + // Microcode + // + reg [UOP_ADDR_WIDTH-1:0] uop_addr; + wire [UOP_DATA_WIDTH-1:0] uop_data; + + wire [4:0] uop_data_opcode = uop_data[1 + 3*6 +: 5]; + wire uop_data_banks = uop_data[0 + 3*6 +: 1]; + wire [5:0] uop_data_operand_src1 = uop_data[0 + 2*6 +: 6]; + wire [5:0] uop_data_operand_src2 = uop_data[0 + 1*6 +: 6]; + wire [5:0] uop_data_operand_dst = uop_data[0 + 0*6 +: 6]; + + wire uop_data_opcode_is_stop = uop_data_opcode[4]; + wire uop_data_opcode_is_mul = uop_data_opcode[3]; + wire uop_data_opcode_is_sub = uop_data_opcode[2]; + wire uop_data_opcode_is_add = uop_data_opcode[1]; + wire uop_data_opcode_is_copy = uop_data_opcode[0]; + + ed25519_microcode_rom microcode_rom + ( + .clk (clk), + .addr (uop_addr), + .data (uop_data) + ); + + + // + // Microcode Address Increment Logic + // + always @(posedge clk) + // + if (fsm_state_next == FSM_STATE_FETCH) + uop_addr <= (fsm_state == FSM_STATE_IDLE) ? uop_offset : uop_addr + 1'b1; + + + // + // Multi-Word Mover + // + reg mw_mover_ena = 1'b0; + wire mw_mover_rdy; + + wire [WORD_COUNTER_WIDTH-1:0] mw_mover_x_addr; + wire [WORD_COUNTER_WIDTH-1:0] mw_mover_y_addr; + wire [ 32-1:0] mw_mover_x_din; + wire [ 32-1:0] mw_mover_y_dout; + wire mw_mover_y_wren; + + mw_mover # + ( + .WORD_COUNTER_WIDTH (WORD_COUNTER_WIDTH), + .OPERAND_NUM_WORDS (OPERAND_NUM_WORDS) + ) + mw_mover_inst + ( + .clk (clk), + .rst_n (rst_n), + .ena (mw_mover_ena), + .rdy (mw_mover_rdy), + .x_addr (mw_mover_x_addr), + .y_addr (mw_mover_y_addr), + .y_wren (mw_mover_y_wren), + .x_din (mw_mover_x_din), + .y_dout (mw_mover_y_dout) + ); + + + // + // Modular Multiplier + // + reg mod_mul_ena = 1'b0; + wire mod_mul_rdy; + + wire [WORD_COUNTER_WIDTH-1:0] mod_mul_a_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_mul_b_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_mul_p_addr; + wire [ 32-1:0] mod_mul_a_din; + wire [ 32-1:0] mod_mul_b_din; + wire [ 32-1:0] mod_mul_p_dout; + wire mod_mul_p_wren; + + ed25519_modular_multiplier mod_mul_inst + ( + .clk (clk), + .rst_n (rst_n), + .ena (mod_mul_ena), + .rdy (mod_mul_rdy), + .a_addr (mod_mul_a_addr), + .b_addr (mod_mul_b_addr), + .p_addr (mod_mul_p_addr), + .p_wren (mod_mul_p_wren), + .a_din (mod_mul_a_din), + .b_din (mod_mul_b_din), + .p_dout (mod_mul_p_dout) + ); + + + // + // Modular Adder + // + reg mod_add_ena = 1'b0; + wire mod_add_rdy; + + wire [WORD_COUNTER_WIDTH-1:0] mod_add_ab_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_add_n_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_add_s_addr; + wire [ 32-1:0] mod_add_a_din; + wire [ 32-1:0] mod_add_b_din; + reg [ 32-1:0] mod_add_n_din; + wire [ 32-1:0] mod_add_s_dout; + wire mod_add_s_wren; + + mod_adder # + ( + .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), + .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) + ) + mod_add_inst + ( + .clk (clk), + .rst_n (rst_n), + .ena (mod_add_ena), + .rdy (mod_add_rdy), + .ab_addr (mod_add_ab_addr), + .n_addr (mod_add_n_addr), + .s_addr (mod_add_s_addr), + .s_wren (mod_add_s_wren), + .a_din (mod_add_a_din), + .b_din (mod_add_b_din), + .n_din (mod_add_n_din), + .s_dout (mod_add_s_dout) + ); + + + // + // Modular Subtractor + // + reg mod_sub_ena = 1'b0; + wire mod_sub_rdy; + + wire [WORD_COUNTER_WIDTH-1:0] mod_sub_ab_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_sub_n_addr; + wire [WORD_COUNTER_WIDTH-1:0] mod_sub_d_addr; + wire [ 32-1:0] mod_sub_a_din; + wire [ 32-1:0] mod_sub_b_din; + reg [ 32-1:0] mod_sub_n_din; + wire [ 32-1:0] mod_sub_d_dout; + wire mod_sub_d_wren; + + mod_subtractor # + ( + .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), + .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) + ) + mod_sub_inst + ( + .clk (clk), + .rst_n (rst_n), + .ena (mod_sub_ena), + .rdy (mod_sub_rdy), + .ab_addr (mod_sub_ab_addr), + .n_addr (mod_sub_n_addr), + .d_addr (mod_sub_d_addr), + .d_wren (mod_sub_d_wren), + .a_din (mod_sub_a_din), + .b_din (mod_sub_b_din), + .n_din (mod_sub_n_din), + .d_dout (mod_sub_d_dout) + ); + + + // + // Double Modulus + // + always @(posedge clk) begin + // + case (mod_add_n_addr) + 3'd0: mod_add_n_din <= !final_reduce ? 32'hFFFFFFDA : 32'hFFFFFFED; + 3'd7: mod_add_n_din <= !final_reduce ? 32'hFFFFFFFF : 32'h7FFFFFFF; + default: mod_add_n_din <= 32'hFFFFFFFF; + endcase + // + if (mod_sub_n_addr == 3'd0) mod_sub_n_din <= 32'hFFFFFFDA; + else mod_sub_n_din <= 32'hFFFFFFFF; + // + end + + + // + // uOP Trigger Logic + // + always @(posedge clk) + // + if (fsm_state == FSM_STATE_DECODE) begin + mw_mover_ena <= uop_data_opcode_is_copy; + mod_mul_ena <= uop_data_opcode_is_mul; + mod_add_ena <= uop_data_opcode_is_add; + mod_sub_ena <= uop_data_opcode_is_sub; + end else begin + mw_mover_ena <= 1'b0; + mod_mul_ena <= 1'b0; + mod_add_ena <= 1'b0; + mod_sub_ena <= 1'b0; + end + + + // + // uOP Completion Detector + // + reg fsm_exit_from_busy; + + always @* begin + // + fsm_exit_from_busy = 0; + // + if (uop_data_opcode_is_copy) fsm_exit_from_busy = ~mw_mover_ena & mw_mover_rdy; + if (uop_data_opcode_is_mul) fsm_exit_from_busy = ~mod_mul_ena & mod_mul_rdy; + if (uop_data_opcode_is_add) fsm_exit_from_busy = ~mod_add_ena & mod_add_rdy; + if (uop_data_opcode_is_sub) fsm_exit_from_busy = ~mod_sub_ena & mod_sub_rdy; + // + end + + + + // + // Banks + // + reg [ 2:0] banks_src1_addr; + reg [ 2:0] banks_src2_addr; + reg [ 2:0] banks_dst_addr; + + reg banks_dst_wren; + + reg [31:0] banks_dst_din; + + wire [31:0] banks_src1_dout; + wire [31:0] banks_src2_dout; + + ed25519_banks_array banks_array + ( + .clk (clk), + + .banks (uop_data_banks), + + .src1_operand (uop_data_operand_src1), + .src2_operand (uop_data_operand_src2), + .dst_operand (uop_data_operand_dst), + + .src1_addr (banks_src1_addr), + .src2_addr (banks_src2_addr), + .dst_addr (banks_dst_addr), + + .dst_wren (banks_dst_wren), + + .src1_dout (banks_src1_dout), + .src2_dout (banks_src2_dout), + + .dst_din (banks_dst_din) + ); + + assign mw_mover_x_din = banks_src1_dout; + assign mod_mul_a_din = banks_src1_dout; + assign mod_mul_b_din = banks_src2_dout; + assign mod_add_a_din = banks_src1_dout; + assign mod_add_b_din = banks_src2_dout; + assign mod_sub_a_din = banks_src1_dout; + assign mod_sub_b_din = banks_src2_dout; + + always @* + // + case (uop_data_opcode) + // + UOP_OPCODE_COPY: begin + // + banks_src1_addr = mw_mover_x_addr; + banks_src2_addr = 'bX; + // + banks_dst_addr = mw_mover_y_addr; + // + banks_dst_wren = mw_mover_y_wren; + // + banks_dst_din = mw_mover_y_dout; + // + end + // + UOP_OPCODE_ADD: begin + // + banks_src1_addr = mod_add_ab_addr; + banks_src2_addr = mod_add_ab_addr; + // + banks_dst_addr = mod_add_s_addr; + // + banks_dst_wren = mod_add_s_wren; + // + banks_dst_din = mod_add_s_dout; + // + end + // + UOP_OPCODE_SUB: begin + // + banks_src1_addr = mod_sub_ab_addr; + banks_src2_addr = mod_sub_ab_addr; + // + banks_dst_addr = mod_sub_d_addr; + // + banks_dst_wren = mod_sub_d_wren; + // + banks_dst_din = mod_sub_d_dout; + // + end + // + UOP_OPCODE_MUL: begin + // + banks_src1_addr = mod_mul_a_addr; + banks_src2_addr = mod_mul_b_addr; + // + banks_dst_addr = mod_mul_p_addr; + // + banks_dst_wren = mod_mul_p_wren; + // + banks_dst_din = mod_mul_p_dout; + // + end + // + default: begin + // + banks_src1_addr = 'bX; + banks_src2_addr = 'bX; + // + banks_dst_addr = 'bX; + // + banks_dst_wren = 'b0; + // + banks_dst_din = 'bX; + end + // + endcase + + + // + // Sign Handler + // + reg sign_x_int; + + wire [31:0] mw_mover_y_dout_with_x_sign = {(mw_mover_y_addr == 3'd7) ? + sign_x_int : mw_mover_y_dout[31], mw_mover_y_dout[30:0]}; + + always @(posedge clk) + // + if (handle_sign && mw_mover_y_wren && (mw_mover_y_addr == 0)) + sign_x_int <= mw_mover_y_dout[0]; + + + // + // FSM Process + // + always @(posedge clk or negedge rst_n) + // + if (rst_n == 1'b0) fsm_state <= FSM_STATE_IDLE; + else fsm_state <= fsm_state_next; + + + // + // FSM Transition Logic + // + always @* begin + // + fsm_state_next = FSM_STATE_IDLE; + // + case (fsm_state) + FSM_STATE_IDLE: fsm_state_next = ena ? FSM_STATE_FETCH : FSM_STATE_IDLE; + FSM_STATE_FETCH: fsm_state_next = FSM_STATE_DECODE; + FSM_STATE_DECODE: fsm_state_next = uop_data_opcode_is_stop ? FSM_STATE_IDLE : FSM_STATE_BUSY; + FSM_STATE_BUSY: fsm_state_next = fsm_exit_from_busy ? FSM_STATE_FETCH : FSM_STATE_BUSY; + endcase + // + end + + + // + // Ready Flag Logic + // + reg rdy_reg = 1'b1; + assign rdy = rdy_reg; + + always @(posedge clk or negedge rst_n) + // + if (rst_n == 1'b0) rdy_reg <= 1'b1; + else case (fsm_state) + FSM_STATE_IDLE: rdy_reg <= ~ena; + FSM_STATE_DECODE: rdy_reg <= uop_data_opcode_is_stop; + endcase + + + + // + // Output Logic + // + reg [ 2: 0] y_addr_reg = 3'b000; + reg [31: 0] y_dout_reg = 32'h00000000; + reg y_wren_reg = 1'b0; + + assign y_addr = y_addr_reg; + assign y_dout = y_dout_reg; + assign y_wren = y_wren_reg; + + always @(posedge clk) + // + if (output_now && mw_mover_y_wren) begin + // + y_addr_reg <= mw_mover_y_addr; + y_dout_reg <= mw_mover_y_dout_with_x_sign; + y_wren_reg <= 1'b1; + // + end else begin + y_addr_reg <= 3'b000; + y_dout_reg <= 32'h00000000; + y_wren_reg <= 1'b0; + end + +endmodule + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/rtl/ed25519_worker.v b/rtl/ed25519_worker.v deleted file mode 100644 index be8152e..0000000 --- a/rtl/ed25519_worker.v +++ /dev/null @@ -1,549 +0,0 @@ -//------------------------------------------------------------------------------ -// -// ed25519_uop_worker.v -// ----------------------------------------------------------------------------- -// Ed25519 uOP Worker. -// -// Authors: Pavel Shatov -// -// Copyright (c) 2018, NORDUnet A/S -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//------------------------------------------------------------------------------ - -module ed25519_worker -( - clk, rst_n, - ena, rdy, - uop_offset, - final_reduce, - handle_sign, - output_now, - y_addr, y_dout, y_wren, - debug_dump_now, - debug_dump_addr1, - debug_dump_addr2, - debug_dump_addr3, - debug_dump_addr4, - debug_dump_addr5, - debug_dump_addr6, - debug_dump_addr7, - debug_dump_addr8 -); - - - // - // Microcode Header - // -`include "ed25519_uop.v" - - - // - // Ports - // - input clk; // system clock - input rst_n; // active-low async reset - - input ena; // enable input - output rdy; // ready output - - input [UOP_ADDR_WIDTH-1:0] uop_offset; // starting offset - - input final_reduce; // use regular (not double) modulus - input handle_sign; // handle sign of x - input output_now; // produce output - - output [ 2: 0] y_addr; - output [31: 0] y_dout; - output y_wren; - - input debug_dump_now; - input [6:0] debug_dump_addr1; - input [6:0] debug_dump_addr2; - input [6:0] debug_dump_addr3; - input [6:0] debug_dump_addr4; - input [6:0] debug_dump_addr5; - input [6:0] debug_dump_addr6; - input [6:0] debug_dump_addr7; - input [6:0] debug_dump_addr8; - - - // - // Constants - // - localparam integer OPERAND_NUM_WORDS = 8; // 256 bits -> 8 x 32-bit words - localparam integer WORD_COUNTER_WIDTH = 3; // 0..7 -> 3 bits - - - // - // FSM - // - localparam [1:0] FSM_STATE_IDLE = 2'b00; - localparam [1:0] FSM_STATE_FETCH = 2'b01; - localparam [1:0] FSM_STATE_DECODE = 2'b10; - localparam [1:0] FSM_STATE_BUSY = 2'b11; - - reg [1:0] fsm_state = FSM_STATE_IDLE; - reg [1:0] fsm_state_next; - - - // - // Microcode - // - reg [UOP_ADDR_WIDTH-1:0] uop_addr; - wire [UOP_DATA_WIDTH-1:0] uop_data; - - wire [4:0] uop_data_opcode = uop_data[1 + 3*6 +: 5]; - wire uop_data_banks = uop_data[0 + 3*6 +: 1]; - wire [5:0] uop_data_operand_src1 = uop_data[0 + 2*6 +: 6]; - wire [5:0] uop_data_operand_src2 = uop_data[0 + 1*6 +: 6]; - wire [5:0] uop_data_operand_dst = uop_data[0 + 0*6 +: 6]; - - wire uop_data_opcode_is_stop = uop_data_opcode[4]; - wire uop_data_opcode_is_mul = uop_data_opcode[3]; - wire uop_data_opcode_is_sub = uop_data_opcode[2]; - wire uop_data_opcode_is_add = uop_data_opcode[1]; - wire uop_data_opcode_is_copy = uop_data_opcode[0]; - - ed25519_microcode microcode - ( - .clk (clk), - .addr (uop_addr), - .data (uop_data) - ); - - - // - // Microcode Address Increment Logic - // - always @(posedge clk) - // - if (fsm_state_next == FSM_STATE_FETCH) - uop_addr <= (fsm_state == FSM_STATE_IDLE) ? uop_offset : uop_addr + 1'b1; - - - // - // Multi-Word Mover - // - reg mw_mover_ena = 1'b0; - wire mw_mover_rdy; - - wire [WORD_COUNTER_WIDTH-1:0] mw_mover_x_addr; - wire [WORD_COUNTER_WIDTH-1:0] mw_mover_y_addr; - wire [ 32-1:0] mw_mover_x_din; - wire [ 32-1:0] mw_mover_y_dout; - wire mw_mover_y_wren; - - mw_mover # - ( - .WORD_COUNTER_WIDTH (WORD_COUNTER_WIDTH), - .OPERAND_NUM_WORDS (OPERAND_NUM_WORDS) - ) - mw_mover_inst - ( - .clk (clk), - .rst_n (rst_n), - .ena (mw_mover_ena), - .rdy (mw_mover_rdy), - .x_addr (mw_mover_x_addr), - .y_addr (mw_mover_y_addr), - .y_wren (mw_mover_y_wren), - .x_din (mw_mover_x_din), - .y_dout (mw_mover_y_dout) - ); - - - // - // Modular Multiplier - // - reg mod_mul_ena = 1'b0; - wire mod_mul_rdy; - - wire [WORD_COUNTER_WIDTH-1:0] mod_mul_a_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_mul_b_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_mul_p_addr; - wire [ 32-1:0] mod_mul_a_din; - wire [ 32-1:0] mod_mul_b_din; - wire [ 32-1:0] mod_mul_p_dout; - wire mod_mul_p_wren; - - ed25519_modular_multiplier mod_mul_inst - ( - .clk (clk), - .rst_n (rst_n), - .ena (mod_mul_ena), - .rdy (mod_mul_rdy), - .a_addr (mod_mul_a_addr), - .b_addr (mod_mul_b_addr), - .p_addr (mod_mul_p_addr), - .p_wren (mod_mul_p_wren), - .a_din (mod_mul_a_din), - .b_din (mod_mul_b_din), - .p_dout (mod_mul_p_dout) - ); - - - // - // Modular Adder - // - reg mod_add_ena = 1'b0; - wire mod_add_rdy; - - wire [WORD_COUNTER_WIDTH-1:0] mod_add_ab_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_add_n_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_add_s_addr; - wire [ 32-1:0] mod_add_a_din; - wire [ 32-1:0] mod_add_b_din; - reg [ 32-1:0] mod_add_n_din; - wire [ 32-1:0] mod_add_s_dout; - wire mod_add_s_wren; - - mod_adder # - ( - .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), - .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) - ) - mod_add_inst - ( - .clk (clk), - .rst_n (rst_n), - .ena (mod_add_ena), - .rdy (mod_add_rdy), - .ab_addr (mod_add_ab_addr), - .n_addr (mod_add_n_addr), - .s_addr (mod_add_s_addr), - .s_wren (mod_add_s_wren), - .a_din (mod_add_a_din), - .b_din (mod_add_b_din), - .n_din (mod_add_n_din), - .s_dout (mod_add_s_dout) - ); - - - // - // Modular Subtractor - // - reg mod_sub_ena = 1'b0; - wire mod_sub_rdy; - - wire [WORD_COUNTER_WIDTH-1:0] mod_sub_ab_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_sub_n_addr; - wire [WORD_COUNTER_WIDTH-1:0] mod_sub_d_addr; - wire [ 32-1:0] mod_sub_a_din; - wire [ 32-1:0] mod_sub_b_din; - reg [ 32-1:0] mod_sub_n_din; - wire [ 32-1:0] mod_sub_d_dout; - wire mod_sub_d_wren; - - mod_subtractor # - ( - .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), - .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) - ) - mod_sub_inst - ( - .clk (clk), - .rst_n (rst_n), - .ena (mod_sub_ena), - .rdy (mod_sub_rdy), - .ab_addr (mod_sub_ab_addr), - .n_addr (mod_sub_n_addr), - .d_addr (mod_sub_d_addr), - .d_wren (mod_sub_d_wren), - .a_din (mod_sub_a_din), - .b_din (mod_sub_b_din), - .n_din (mod_sub_n_din), - .d_dout (mod_sub_d_dout) - ); - - - // - // Double Modulus - // - always @(posedge clk) begin - // - case (mod_add_n_addr) - 3'd0: mod_add_n_din <= !final_reduce ? 32'hFFFFFFDA : 32'hFFFFFFED; - 3'd7: mod_add_n_din <= !final_reduce ? 32'hFFFFFFFF : 32'h7FFFFFFF; - default: mod_add_n_din <= 32'hFFFFFFFF; - endcase - // - if (mod_sub_n_addr == 3'd0) mod_sub_n_din <= 32'hFFFFFFDA; - else mod_sub_n_din <= 32'hFFFFFFFF; - // - end - - - // - // uOP Trigger Logic - // - always @(posedge clk) - // - if (fsm_state == FSM_STATE_DECODE) begin - mw_mover_ena <= uop_data_opcode_is_copy; - mod_mul_ena <= uop_data_opcode_is_mul; - mod_add_ena <= uop_data_opcode_is_add; - mod_sub_ena <= uop_data_opcode_is_sub; - end else begin - mw_mover_ena <= 1'b0; - mod_mul_ena <= 1'b0; - mod_add_ena <= 1'b0; - mod_sub_ena <= 1'b0; - end - - - // - // uOP Completion Detector - // - reg fsm_exit_from_busy; - - always @* begin - // - fsm_exit_from_busy = 0; - // - if (uop_data_opcode_is_copy) fsm_exit_from_busy = ~mw_mover_ena & mw_mover_rdy; - if (uop_data_opcode_is_mul) fsm_exit_from_busy = ~mod_mul_ena & mod_mul_rdy; - if (uop_data_opcode_is_add) fsm_exit_from_busy = ~mod_add_ena & mod_add_rdy; - if (uop_data_opcode_is_sub) fsm_exit_from_busy = ~mod_sub_ena & mod_sub_rdy; - // - end - - - - // - // Banks - // - reg [ 2:0] banks_src1_addr; - reg [ 2:0] banks_src2_addr; - reg [ 2:0] banks_dst_addr; - - reg banks_dst_wren; - - reg [31:0] banks_dst_din; - - wire [31:0] banks_src1_dout; - wire [31:0] banks_src2_dout; - - ed25519_banks banks - ( - .clk (clk), - - .banks (uop_data_banks), - - .src1_operand (uop_data_operand_src1), - .src2_operand (uop_data_operand_src2), - .dst_operand (uop_data_operand_dst), - - .src1_addr (banks_src1_addr), - .src2_addr (banks_src2_addr), - .dst_addr (banks_dst_addr), - - .dst_wren (banks_dst_wren), - - .src1_dout (banks_src1_dout), - .src2_dout (banks_src2_dout), - - .dst_din (banks_dst_din), - - .debug_dump_now(debug_dump_now), - .debug_dump_addr1(debug_dump_addr1), - .debug_dump_addr2(debug_dump_addr2), - .debug_dump_addr3(debug_dump_addr3), - .debug_dump_addr4(debug_dump_addr4), - .debug_dump_addr5(debug_dump_addr5), - .debug_dump_addr6(debug_dump_addr6), - .debug_dump_addr7(debug_dump_addr7), - .debug_dump_addr8(debug_dump_addr8) - ); - - assign mw_mover_x_din = banks_src1_dout; - assign mod_mul_a_din = banks_src1_dout; - assign mod_mul_b_din = banks_src2_dout; - assign mod_add_a_din = banks_src1_dout; - assign mod_add_b_din = banks_src2_dout; - assign mod_sub_a_din = banks_src1_dout; - assign mod_sub_b_din = banks_src2_dout; - - always @* - // - case (uop_data_opcode) - // - UOP_OPCODE_COPY: begin - // - banks_src1_addr = mw_mover_x_addr; - banks_src2_addr = 'bX; - // - banks_dst_addr = mw_mover_y_addr; - // - banks_dst_wren = mw_mover_y_wren; - // - banks_dst_din = mw_mover_y_dout; - // - end - // - UOP_OPCODE_ADD: begin - // - banks_src1_addr = mod_add_ab_addr; - banks_src2_addr = mod_add_ab_addr; - // - banks_dst_addr = mod_add_s_addr; - // - banks_dst_wren = mod_add_s_wren; - // - banks_dst_din = mod_add_s_dout; - // - end - // - UOP_OPCODE_SUB: begin - // - banks_src1_addr = mod_sub_ab_addr; - banks_src2_addr = mod_sub_ab_addr; - // - banks_dst_addr = mod_sub_d_addr; - // - banks_dst_wren = mod_sub_d_wren; - // - banks_dst_din = mod_sub_d_dout; - // - end - // - UOP_OPCODE_MUL: begin - // - banks_src1_addr = mod_mul_a_addr; - banks_src2_addr = mod_mul_b_addr; - // - banks_dst_addr = mod_mul_p_addr; - // - banks_dst_wren = mod_mul_p_wren; - // - banks_dst_din = mod_mul_p_dout; - // - end - // - default: begin - // - banks_src1_addr = 'bX; - banks_src2_addr = 'bX; - // - banks_dst_addr = 'bX; - // - banks_dst_wren = 'b0; - // - banks_dst_din = 'bX; - end - // - endcase - - - // - // Sign Handler - // - reg sign_x_int; - - wire [31:0] mw_mover_y_dout_with_x_sign = {(mw_mover_y_addr == 3'd7) ? - sign_x_int : mw_mover_y_dout[31], mw_mover_y_dout[30:0]}; - - always @(posedge clk) - // - if (handle_sign && mw_mover_y_wren && (mw_mover_y_addr == 0)) - sign_x_int <= mw_mover_y_dout[0]; - - - // - // FSM Process - // - always @(posedge clk or negedge rst_n) - // - if (rst_n == 1'b0) fsm_state <= FSM_STATE_IDLE; - else fsm_state <= fsm_state_next; - - - // - // FSM Transition Logic - // - always @* begin - // - fsm_state_next = FSM_STATE_IDLE; - // - case (fsm_state) - FSM_STATE_IDLE: fsm_state_next = ena ? FSM_STATE_FETCH : FSM_STATE_IDLE; - FSM_STATE_FETCH: fsm_state_next = FSM_STATE_DECODE; - FSM_STATE_DECODE: fsm_state_next = uop_data_opcode_is_stop ? FSM_STATE_IDLE : FSM_STATE_BUSY; - FSM_STATE_BUSY: fsm_state_next = fsm_exit_from_busy ? FSM_STATE_FETCH : FSM_STATE_BUSY; - endcase - // - end - - - // - // Ready Flag Logic - // - reg rdy_reg = 1'b1; - assign rdy = rdy_reg; - - always @(posedge clk or negedge rst_n) - // - if (rst_n == 1'b0) rdy_reg <= 1'b1; - else case (fsm_state) - FSM_STATE_IDLE: rdy_reg <= ~ena; - FSM_STATE_DECODE: rdy_reg <= uop_data_opcode_is_stop; - endcase - - - - // - // Output Logic - // - reg [ 2: 0] y_addr_reg = 3'b000; - reg [31: 0] y_dout_reg = 32'h00000000; - reg y_wren_reg = 1'b0; - - assign y_addr = y_addr_reg; - assign y_dout = y_dout_reg; - assign y_wren = y_wren_reg; - - always @(posedge clk) - // - if (output_now && mw_mover_y_wren) begin - // - y_addr_reg <= mw_mover_y_addr; - y_dout_reg <= mw_mover_y_dout_with_x_sign; - y_wren_reg <= 1'b1; - // - end else begin - y_addr_reg <= 3'b000; - y_dout_reg <= 32'h00000000; - y_wren_reg <= 1'b0; - end - -endmodule - - -//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------ -- cgit v1.2.3