1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
|
`timescale 1ns / 1ps
module modinv_helper_invert_update
(
clk, rst_n,
ena, rdy,
u_gt_v, v_eq_1,
u_is_even, v_is_even,
r_addr, r_wren, r_dout,
s_addr, s_wren, s_dout,
u_addr, u_wren, u_dout,
v_addr, v_wren, v_dout,
r_dbl_addr, r_dbl_din,
s_dbl_addr, s_dbl_din,
r_plus_s_addr, r_plus_s_din,
u_half_addr, u_half_din,
v_half_addr, v_half_din,
u_minus_v_half_addr, u_minus_v_half_din,
v_minus_u_half_addr, v_minus_u_half_din
);
//
// Parameters
//
parameter BUFFER_NUM_WORDS = 9;
parameter BUFFER_ADDR_BITS = 4;
//
// clog2
//
`include "..\modinv_clog2.v"
//
// Constants
//
localparam PROC_NUM_CYCLES = BUFFER_NUM_WORDS + 3;
localparam PROC_CNT_BITS = clog2(PROC_NUM_CYCLES);
//
// Ports
//
input wire clk;
input wire rst_n;
input wire ena;
output wire rdy;
input wire u_gt_v;
input wire v_eq_1;
input wire u_is_even;
input wire v_is_even;
output wire [BUFFER_ADDR_BITS-1:0] r_addr;
output wire [BUFFER_ADDR_BITS-1:0] s_addr;
output wire [BUFFER_ADDR_BITS-1:0] u_addr;
output wire [BUFFER_ADDR_BITS-1:0] v_addr;
output wire r_wren;
output wire s_wren;
output wire u_wren;
output wire v_wren;
output wire [ 32-1:0] r_dout;
output wire [ 32-1:0] s_dout;
output wire [ 32-1:0] u_dout;
output wire [ 32-1:0] v_dout;
output wire [BUFFER_ADDR_BITS-1:0] r_dbl_addr;
output wire [BUFFER_ADDR_BITS-1:0] s_dbl_addr;
output wire [BUFFER_ADDR_BITS-1:0] r_plus_s_addr;
output wire [BUFFER_ADDR_BITS-1:0] u_half_addr;
output wire [BUFFER_ADDR_BITS-1:0] v_half_addr;
output wire [BUFFER_ADDR_BITS-1:0] u_minus_v_half_addr;
output wire [BUFFER_ADDR_BITS-1:0] v_minus_u_half_addr;
input wire [ 32-1:0] r_dbl_din;
input wire [ 32-1:0] s_dbl_din;
input wire [ 32-1:0] r_plus_s_din;
input wire [ 32-1:0] u_half_din;
input wire [ 32-1:0] v_half_din;
input wire [ 32-1:0] u_minus_v_half_din;
input wire [ 32-1:0] v_minus_u_half_din;
//
// Counter
//
reg [PROC_CNT_BITS-1:0] proc_cnt;
wire [PROC_CNT_BITS-1:0] proc_cnt_max = PROC_NUM_CYCLES - 1;
wire [PROC_CNT_BITS-1:0] proc_cnt_zero = {PROC_CNT_BITS{1'b0}};
wire [PROC_CNT_BITS-1:0] proc_cnt_next = (proc_cnt < proc_cnt_max) ?
proc_cnt + 1'b1 : proc_cnt_zero;
//
// Addresses
//
reg [BUFFER_ADDR_BITS-1:0] addr_in;
wire [BUFFER_ADDR_BITS-1:0] addr_in_max = BUFFER_NUM_WORDS - 1;
wire [BUFFER_ADDR_BITS-1:0] addr_in_zero = {BUFFER_ADDR_BITS{1'b0}};
wire [BUFFER_ADDR_BITS-1:0] addr_in_next = (addr_in < addr_in_max) ?
addr_in + 1'b1 : addr_in_zero;
reg [BUFFER_ADDR_BITS-1:0] addr_out;
wire [BUFFER_ADDR_BITS-1:0] addr_out_max = BUFFER_NUM_WORDS - 1;
wire [BUFFER_ADDR_BITS-1:0] addr_out_zero = {BUFFER_ADDR_BITS{1'b0}};
wire [BUFFER_ADDR_BITS-1:0] addr_out_next = (addr_out < addr_out_max) ?
addr_out + 1'b1 : addr_out_zero;
assign r_addr = addr_out;
assign s_addr = addr_out;
assign u_addr = addr_out;
assign v_addr = addr_out;
assign r_dbl_addr = addr_in;
assign s_dbl_addr = addr_in;
assign r_plus_s_addr = addr_in;
assign u_half_addr = addr_in;
assign v_half_addr = addr_in;
assign u_minus_v_half_addr = addr_in;
assign v_minus_u_half_addr = addr_in;
//
// Ready Flag
//
assign rdy = (proc_cnt == proc_cnt_zero);
//
// Address Increment Logic
//
wire inc_addr_in;
wire inc_addr_out;
wire [PROC_CNT_BITS-1:0] cnt_inc_addr_in_start = 1;
wire [PROC_CNT_BITS-1:0] cnt_inc_addr_in_stop = BUFFER_NUM_WORDS;
wire [PROC_CNT_BITS-1:0] cnt_inc_addr_out_start = 2;
wire [PROC_CNT_BITS-1:0] cnt_inc_addr_out_stop = BUFFER_NUM_WORDS + 1;
assign inc_addr_in = (proc_cnt >= cnt_inc_addr_in_start) && (proc_cnt <= cnt_inc_addr_in_stop);
assign inc_addr_out = (proc_cnt >= cnt_inc_addr_out_start) && (proc_cnt <= cnt_inc_addr_out_stop);
always @(posedge clk) begin
//
if (inc_addr_in) addr_in <= addr_in_next;
else addr_in <= addr_in_zero;
//
if (inc_addr_out) addr_out <= addr_out_next;
else addr_out <= addr_out_zero;
//
end
//
// Write Enable Logic
//
wire wren_out;
wire [PROC_CNT_BITS-1:0] cnt_wren_out_start = 2;
wire [PROC_CNT_BITS-1:0] cnt_wren_out_stop = BUFFER_NUM_WORDS + 1;
assign wren_out = (proc_cnt >= cnt_wren_out_start) && (proc_cnt <= cnt_wren_out_stop);
reg r_wren_allow;
reg s_wren_allow;
reg u_wren_allow;
reg v_wren_allow;
assign r_wren = wren_out && r_wren_allow && !v_eq_1 && !rdy;
assign s_wren = wren_out && s_wren_allow && !v_eq_1 && !rdy;
assign u_wren = wren_out && u_wren_allow && !v_eq_1 && !rdy;
assign v_wren = wren_out && v_wren_allow && !v_eq_1 && !rdy;
//
// Data Logic
//
reg [31: 0] r_dout_mux;
reg [31: 0] s_dout_mux;
reg [31: 0] u_dout_mux;
reg [31: 0] v_dout_mux;
assign r_dout = r_dout_mux;
assign s_dout = s_dout_mux;
assign u_dout = u_dout_mux;
assign v_dout = v_dout_mux;
always @(*) begin
//
// r, s, u, v
//
if (u_is_even) begin
//
u_dout_mux = u_half_din;
v_dout_mux = {32{1'bX}};
r_dout_mux = {32{1'bX}};
s_dout_mux = s_dbl_din;
//
u_wren_allow = 1'b1;
v_wren_allow = 1'b0;
r_wren_allow = 1'b0;
s_wren_allow = 1'b1;
//
end else begin
//
if (v_is_even) begin
//
u_dout_mux = {32{1'bX}};
v_dout_mux = v_half_din;
r_dout_mux = r_dbl_din;
s_dout_mux = {32{1'bX}};
//
u_wren_allow = 1'b0;
v_wren_allow = 1'b1;
r_wren_allow = 1'b1;
s_wren_allow = 1'b0;
//
end else begin
//
u_dout_mux = u_gt_v ? u_minus_v_half_din : {32{1'bX}};
v_dout_mux = u_gt_v ? {32{1'bX}} : v_minus_u_half_din;
r_dout_mux = u_gt_v ? r_plus_s_din : r_dbl_din;
s_dout_mux = u_gt_v ? s_dbl_din : r_plus_s_din;
//
u_wren_allow = u_gt_v;
v_wren_allow = !u_gt_v;
r_wren_allow = 1'b1;
s_wren_allow = 1'b1;
//
end
//
end
//
end
//
// Primary Counter Logic
//
always @(posedge clk or negedge rst_n)
//
if (rst_n == 1'b0) proc_cnt <= proc_cnt_zero;
else begin
if (!rdy) proc_cnt <= proc_cnt_next;
else if (ena) proc_cnt <= proc_cnt_next;
end
endmodule
|
