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core for better timing performance
* Removed custom modular inversion sub-module, now uses micro-coded modular
inversion routine based on Fermat's little theorem (~10% faster)
* Uses math primitives from core/lib
* Added randomized test vector
(see user/shatov/ecdsa_fpga_model/test_vectors/)
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Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.
Code common between this core and the ecdsa384 core split out into a
separate library repository.
Minor cleanup (Windows-isms, indentation).
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* Added sample C program for STM32 to test the core in hardware
* Parametrized math modules are now instantiated with explicit
operand width for clarify (previously relied on default
parameter values in underlying modules)
* Fixed some comments
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