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AgeCommit message (Collapse)Author
2018-09-06Replicated certain FSM-related signals for better placement and routing.Pavel V. Shatov (Meister)
2018-09-06Turned ROMs into distributed memories, otherwise synthesizer was combining themPavel V. Shatov (Meister)
into a single block ROM which hurt placement and routing.
2018-04-17Modified the test program to verify that changes in Verilog do work.fixPavel V. Shatov (Meister)
2018-04-01Added more test vectors to trigger the virtually never taken path in the curvePavel V. Shatov (Meister)
point addition routine.
2018-04-01Fixed coordinates of the internally stored point H = 2 * G.Pavel V. Shatov (Meister)
2018-04-01Minor cleanup.Pavel V. Shatov (Meister)
2017-03-07Promote to a repository in the core tree.Rob Austein
Change name of reset signal from rst_n to reset_n for consistancy with other Cryptech cores. Code common between this core and the ecdsa384 core split out into a separate library repository. Minor cleanup (Windows-isms, indentation).
2017-02-12Various clean-upsPavel V. Shatov (Meister)
* Added sample C program for STM32 to test the core in hardware * Parametrized math modules are now instantiated with explicit operand width for clarify (previously relied on default parameter values in underlying modules) * Fixed some comments
2016-12-04Added README.md with core description, API details, etcPavel V. Shatov (Meister)
Added previously forgotten generic replacements for vendor-specific primitives Minor clean up of comments Slightly reduced power consumption
2016-10-31Initial commit of base point multiplier core for ECDSA curve P-256.Pavel V. Shatov (Meister)