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BranchCommit messageAuthorAge
fixModified the test program to verify that changes in Verilog do work.Pavel V. Shatov (Meister)6 years
master * Rewritten from scratch, uses the same hardware architecture as the Ed25519Pavel V. Shatov (Meister)5 years
test_dpa_fixFixed copyright notices.Pavel V. Shatov (Meister)3 years
 
 
AgeCommit messageAuthor
2021-07-19Fixed copyright notices.test_dpa_fixPavel V. Shatov (Meister)
2021-04-12New testbench (basically the same as tb_curve_multiplier_256.v, but testsPavel V. Shatov (Meister)
2021-04-12Cleaned up wrapper modulePavel V. Shatov (Meister)
2021-04-12Ported FSM in the top-level modulePavel V. Shatov (Meister)
2021-04-12Ported microcode "worker" modulePavel V. Shatov (Meister)
2021-04-12New microcode source for Montgomery ladder variantPavel V. Shatov (Meister)
2018-12-19 * Rewritten from scratch, uses the same hardware architecture as the Ed25519HEADmasterPavel V. Shatov (Meister)
2018-09-06Replicated certain FSM-related signals for better placement and routing.Pavel V. Shatov (Meister)
2018-09-06Turned ROMs into distributed memories, otherwise synthesizer was combining themPavel V. Shatov (Meister)
2018-04-17Modified the test program to verify that changes in Verilog do work.fixPavel V. Shatov (Meister)
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