diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/ecdsa256_base_point_multiplier.v | 123 |
1 files changed, 64 insertions, 59 deletions
diff --git a/rtl/ecdsa256_base_point_multiplier.v b/rtl/ecdsa256_base_point_multiplier.v index 8664d0c..2adca43 100644 --- a/rtl/ecdsa256_base_point_multiplier.v +++ b/rtl/ecdsa256_base_point_multiplier.v @@ -73,27 +73,25 @@ module ecdsa256_base_point_multiplier // // FSM // - localparam [4:0] FSM_STATE_IDLE = 5'd00; - localparam [4:0] FSM_STATE_PREPARE_TRIG = 5'd01; - localparam [4:0] FSM_STATE_PREPARE_WAIT = 5'd02; - localparam [4:0] FSM_STATE_CYCLE_DBL_TRIG = 5'd03; - localparam [4:0] FSM_STATE_CYCLE_DBL_WAIT = 5'd04; - localparam [4:0] FSM_STATE_CYCLE_ADD_TRIG = 5'd05; - localparam [4:0] FSM_STATE_CYCLE_ADD_WAIT = 5'd06; - localparam [4:0] FSM_STATE_CYCLE_ADD_EXTRA_TRIG = 5'd07; - localparam [4:0] FSM_STATE_CYCLE_ADD_EXTRA_WAIT = 5'd08; - localparam [4:0] FSM_STATE_AFTER_CYCLE_TRIG = 5'd09; - localparam [4:0] FSM_STATE_AFTER_CYCLE_WAIT = 5'd10; - localparam [4:0] FSM_STATE_INVERT_TRIG = 5'd11; - localparam [4:0] FSM_STATE_INVERT_WAIT = 5'd12; - localparam [4:0] FSM_STATE_CONVERT_TRIG = 5'd13; - localparam [4:0] FSM_STATE_CONVERT_WAIT = 5'd14; - localparam [4:0] FSM_STATE_CONVERT_EXTRA_TRIG = 5'd15; - localparam [4:0] FSM_STATE_CONVERT_EXTRA_WAIT = 5'd16; - localparam [4:0] FSM_STATE_DONE = 5'd17; - - reg [4:0] fsm_state = FSM_STATE_IDLE; - reg [4:0] fsm_state_next; + localparam [3:0] FSM_STATE_IDLE = 4'd00; + localparam [3:0] FSM_STATE_PREPARE_TRIG = 4'd01; + localparam [3:0] FSM_STATE_PREPARE_WAIT = 4'd02; + localparam [3:0] FSM_STATE_CYCLE_ADD_TRIG = 4'd03; + localparam [3:0] FSM_STATE_CYCLE_ADD_WAIT = 4'd04; + localparam [3:0] FSM_STATE_CYCLE_ADD_EXTRA_TRIG = 4'd05; + localparam [3:0] FSM_STATE_CYCLE_ADD_EXTRA_WAIT = 4'd06; + localparam [3:0] FSM_STATE_CYCLE_DBL_TRIG = 4'd07; + localparam [3:0] FSM_STATE_CYCLE_DBL_WAIT = 4'd08; + localparam [3:0] FSM_STATE_AFTER_CYCLE_TRIG = 4'd09; + localparam [3:0] FSM_STATE_AFTER_CYCLE_WAIT = 4'd10; + localparam [3:0] FSM_STATE_INVERT_TRIG = 4'd11; + localparam [3:0] FSM_STATE_INVERT_WAIT = 4'd12; + localparam [3:0] FSM_STATE_CONVERT_TRIG = 4'd13; + localparam [3:0] FSM_STATE_CONVERT_WAIT = 4'd14; + localparam [3:0] FSM_STATE_DONE = 4'd15; + + reg [3:0] fsm_state = FSM_STATE_IDLE; + reg [3:0] fsm_state_next; // @@ -121,13 +119,12 @@ module ecdsa256_base_point_multiplier if (rst_n == 1'b0) worker_trig <= 1'b0; else case (fsm_state) FSM_STATE_PREPARE_TRIG, - FSM_STATE_CYCLE_DBL_TRIG, FSM_STATE_CYCLE_ADD_TRIG, FSM_STATE_CYCLE_ADD_EXTRA_TRIG, + FSM_STATE_CYCLE_DBL_TRIG, FSM_STATE_AFTER_CYCLE_TRIG, FSM_STATE_INVERT_TRIG, - FSM_STATE_CONVERT_TRIG, - FSM_STATE_CONVERT_EXTRA_TRIG: worker_trig <= 1'b1; + FSM_STATE_CONVERT_TRIG: worker_trig <= 1'b1; default: worker_trig <= 1'b0; endcase @@ -147,7 +144,7 @@ module ecdsa256_base_point_multiplier // Final Cycle Detection Logic // wire [ 3: 0] fsm_state_after_cycle = (bit_counter == bit_counter_last) ? - FSM_STATE_INVERT_TRIG : FSM_STATE_CYCLE_DBL_TRIG; + FSM_STATE_INVERT_TRIG : FSM_STATE_CYCLE_ADD_TRIG; // @@ -168,16 +165,10 @@ module ecdsa256_base_point_multiplier // // Worker Flags // - wire worker_flagz_sz; - wire worker_flagz_rz; - wire worker_flagz_e; - wire worker_flagz_f; + wire worker_flagz_r0z; + wire worker_flagz_r1z; - wire [2:0] worker_flagz_cycle_add = - {worker_flagz_sz, worker_flagz_e, worker_flagz_f}; - - wire worker_flagz_convert_extra = - worker_flagz_rz; + wire [1:0] worker_flagz_cycle_add = {worker_flagz_r1z, worker_flagz_r0z}; // @@ -191,26 +182,24 @@ module ecdsa256_base_point_multiplier FSM_STATE_PREPARE_TRIG: worker_offset <= UOP_OFFSET_PREPARE; - FSM_STATE_CYCLE_DBL_TRIG: worker_offset <= UOP_OFFSET_CYCLE_DOUBLE; FSM_STATE_CYCLE_ADD_TRIG: worker_offset <= UOP_OFFSET_CYCLE_ADD; - + FSM_STATE_CYCLE_ADD_EXTRA_TRIG: - // {sz, e, f} - casez(worker_flagz_cycle_add) - 3'b1??: worker_offset <= UOP_OFFSET_CYCLE_ADD_AT_INFINITY; - 3'b011: worker_offset <= UOP_OFFSET_CYCLE_ADD_SAME_X_SAME_Y; - 3'b010: worker_offset <= UOP_OFFSET_CYCLE_ADD_SAME_X; - 3'b00?: worker_offset <= UOP_OFFSET_CYCLE_ADD_REGULAR; + // {r1z, r0z} + case (worker_flagz_cycle_add) + 2'b01: worker_offset <= UOP_OFFSET_CYCLE_ADD_R0_AT_INFINITY; + 2'b10: worker_offset <= UOP_OFFSET_CYCLE_ADD_R1_AT_INFINITY; endcase - + + FSM_STATE_CYCLE_DBL_TRIG: worker_offset <= k_din_shreg[31] ? + UOP_OFFSET_CYCLE_DOUBLE_R1 : UOP_OFFSET_CYCLE_DOUBLE_R0; + FSM_STATE_AFTER_CYCLE_TRIG: worker_offset <= k_din_shreg[31] ? UOP_OFFSET_CYCLE_K1 : UOP_OFFSET_CYCLE_K0; FSM_STATE_INVERT_TRIG: worker_offset <= UOP_OFFSET_INVERT; - FSM_STATE_CONVERT_TRIG: worker_offset <= UOP_OFFSET_CONVERT; - FSM_STATE_CONVERT_EXTRA_TRIG: worker_offset <= worker_flagz_convert_extra ? - UOP_OFFSET_CONVERT_AT_INFINITY : UOP_OFFSET_CONVERT_REGULAR; + FSM_STATE_CONVERT_TRIG: worker_offset <= UOP_OFFSET_CONVERT; default: worker_offset <= {UOP_ADDR_WIDTH{1'bX}}; @@ -238,21 +227,24 @@ module ecdsa256_base_point_multiplier FSM_STATE_IDLE: fsm_state_next = ena ? FSM_STATE_PREPARE_TRIG : FSM_STATE_IDLE; FSM_STATE_PREPARE_TRIG: fsm_state_next = FSM_STATE_PREPARE_WAIT ; - FSM_STATE_PREPARE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CYCLE_DBL_TRIG : FSM_STATE_PREPARE_WAIT; - FSM_STATE_CYCLE_DBL_TRIG: fsm_state_next = FSM_STATE_CYCLE_DBL_WAIT ; - FSM_STATE_CYCLE_DBL_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CYCLE_ADD_TRIG : FSM_STATE_CYCLE_DBL_WAIT; + FSM_STATE_PREPARE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CYCLE_ADD_TRIG : FSM_STATE_PREPARE_WAIT; + FSM_STATE_CYCLE_ADD_TRIG: fsm_state_next = FSM_STATE_CYCLE_ADD_WAIT ; FSM_STATE_CYCLE_ADD_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CYCLE_ADD_EXTRA_TRIG : FSM_STATE_CYCLE_ADD_WAIT; + FSM_STATE_CYCLE_ADD_EXTRA_TRIG: fsm_state_next = FSM_STATE_CYCLE_ADD_EXTRA_WAIT ; - FSM_STATE_CYCLE_ADD_EXTRA_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_CYCLE_TRIG : FSM_STATE_CYCLE_ADD_EXTRA_WAIT; + FSM_STATE_CYCLE_ADD_EXTRA_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CYCLE_DBL_TRIG : FSM_STATE_CYCLE_ADD_EXTRA_WAIT; + + FSM_STATE_CYCLE_DBL_TRIG: fsm_state_next = FSM_STATE_CYCLE_DBL_WAIT ; + FSM_STATE_CYCLE_DBL_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_CYCLE_TRIG : FSM_STATE_CYCLE_DBL_WAIT; + FSM_STATE_AFTER_CYCLE_TRIG: fsm_state_next = FSM_STATE_AFTER_CYCLE_WAIT ; FSM_STATE_AFTER_CYCLE_WAIT: fsm_state_next = fsm_wait_done ? fsm_state_after_cycle : FSM_STATE_AFTER_CYCLE_WAIT; FSM_STATE_INVERT_TRIG: fsm_state_next = FSM_STATE_INVERT_WAIT ; FSM_STATE_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CONVERT_TRIG : FSM_STATE_INVERT_WAIT; FSM_STATE_CONVERT_TRIG: fsm_state_next = FSM_STATE_CONVERT_WAIT ; - FSM_STATE_CONVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_CONVERT_EXTRA_TRIG : FSM_STATE_CONVERT_WAIT; - FSM_STATE_CONVERT_EXTRA_TRIG: fsm_state_next = FSM_STATE_CONVERT_EXTRA_WAIT ; - FSM_STATE_CONVERT_EXTRA_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DONE : FSM_STATE_CONVERT_EXTRA_WAIT; + FSM_STATE_CONVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DONE : FSM_STATE_CONVERT_WAIT; + FSM_STATE_DONE: fsm_state_next = FSM_STATE_IDLE ; endcase @@ -263,7 +255,7 @@ module ecdsa256_base_point_multiplier // // Worker // - wire worker_output_now = (fsm_state == FSM_STATE_CONVERT_EXTRA_WAIT); + wire worker_output_now = (fsm_state == FSM_STATE_CONVERT_WAIT); ecdsa256_uop_worker uop_worker ( @@ -275,10 +267,8 @@ module ecdsa256_base_point_multiplier .uop_offset (worker_offset), .output_now (worker_output_now), - .flagz_sz (worker_flagz_sz), - .flagz_rz (worker_flagz_rz), - .flagz_e (worker_flagz_e), - .flagz_f (worker_flagz_f), + .flagz_r0z (worker_flagz_r0z), + .flagz_r1z (worker_flagz_r1z), .xy_addr (rxy_addr), .xy_dout (rxy_dout), @@ -300,7 +290,22 @@ module ecdsa256_base_point_multiplier FSM_STATE_IDLE: if (ena) rdy_reg <= 1'b0; FSM_STATE_DONE: rdy_reg <= 1'b1; endcase - + + + + // + // Debug + // + `ifdef CRYPTECH_DEBUG_ECDSA + + wire zzz; + + always @(posedge clk) + // + if (fsm_state == FSM_STATE_CYCLE_DBL_TRIG) + $display("wc = %d, bc = %d, k_bit = %d", k_addr, k_bit_index, k_din_shreg[31]); + + `endif endmodule |