diff options
Diffstat (limited to 'rtl/curve/rom/brom_p256_delta.v')
-rw-r--r-- | rtl/curve/rom/brom_p256_delta.v | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/rtl/curve/rom/brom_p256_delta.v b/rtl/curve/rom/brom_p256_delta.v index b9a345a..4637575 100644 --- a/rtl/curve/rom/brom_p256_delta.v +++ b/rtl/curve/rom/brom_p256_delta.v @@ -33,36 +33,36 @@ `timescale 1ns / 1ps module brom_p256_delta - ( - input wire clk, - input wire [ 3-1:0] b_addr, - output wire [32-1:0] b_out - ); + ( + input wire clk, + input wire [ 3-1:0] b_addr, + output wire [32-1:0] b_out + ); // // Output Registers // - reg [31:0] bram_reg_b; + reg [31:0] bram_reg_b; assign b_out = bram_reg_b; // // Read-Only Port B - // - always @(posedge clk) - //
- case (b_addr)
- 3'b000: bram_reg_b <= 32'h00000000;
- 3'b001: bram_reg_b <= 32'h00000000;
- 3'b010: bram_reg_b <= 32'h80000000;
- 3'b011: bram_reg_b <= 32'h00000000;
- 3'b100: bram_reg_b <= 32'h00000000;
- 3'b101: bram_reg_b <= 32'h80000000;
- 3'b110: bram_reg_b <= 32'h80000000;
- 3'b111: bram_reg_b <= 32'h7fffffff;
- endcase + // + always @(posedge clk) + // + case (b_addr) + 3'b000: bram_reg_b <= 32'h00000000; + 3'b001: bram_reg_b <= 32'h00000000; + 3'b010: bram_reg_b <= 32'h80000000; + 3'b011: bram_reg_b <= 32'h00000000; + 3'b100: bram_reg_b <= 32'h00000000; + 3'b101: bram_reg_b <= 32'h80000000; + 3'b110: bram_reg_b <= 32'h80000000; + 3'b111: bram_reg_b <= 32'h7fffffff; + endcase endmodule |