diff options
author | Rob Austein <sra@hactrn.net> | 2017-03-07 19:52:36 -0500 |
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committer | Rob Austein <sra@hactrn.net> | 2017-03-07 19:52:36 -0500 |
commit | 89f913c3aa2a6dad35630f3882a06b99e0978105 (patch) | |
tree | a8c05b11c926ad72f10a0c4b798ef4b46912e3bf /rtl/lowlevel/generic/adder47_generic.v | |
parent | 9fa6e368879d30835880b3bb0e87c8cf13dd9874 (diff) |
Promote to a repository in the core tree.
Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.
Code common between this core and the ecdsa384 core split out into a
separate library repository.
Minor cleanup (Windows-isms, indentation).
Diffstat (limited to 'rtl/lowlevel/generic/adder47_generic.v')
-rw-r--r-- | rtl/lowlevel/generic/adder47_generic.v | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/rtl/lowlevel/generic/adder47_generic.v b/rtl/lowlevel/generic/adder47_generic.v deleted file mode 100644 index f472061..0000000 --- a/rtl/lowlevel/generic/adder47_generic.v +++ /dev/null @@ -1,64 +0,0 @@ -//------------------------------------------------------------------------------ -// -// adder47_generic.v -// ----------------------------------------------------------------------------- -// Generic 47-bit adder.
-// -// Authors: Pavel Shatov -// -// Copyright (c) 2016, NORDUnet A/S -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//------------------------------------------------------------------------------
-
-module adder47_generic
- (
- input clk, // clock
- input [46: 0] a, // operand input
- input [46: 0] b, // operand input
- output [46: 0] s // sum output
- );
-
- // - // Sum - // - reg [46: 0] s_int;
-
- always @(posedge clk)
- s_int <= a + b;
-
- //
- // Output
- //
- assign s = s_int;
-
-endmodule
-
-//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------
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