diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:34:55 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:41:00 +0300 |
| commit | c617c0c711620f58eb3ead22edcdfe57fed06088 (patch) | |
| tree | 8c15184d5ca6403ea01843560394f6d909a0986f /rtl/ecdsa256_wrapper.v | |
| parent | ea4d251c81c8b53e0bbc71cd1719dfea4d0517c1 (diff) | |
core for better timing performance
* Removed custom modular inversion sub-module, now uses micro-coded modular
inversion routine based on Fermat's little theorem (~10% faster)
* Uses math primitives from core/lib
* Added randomized test vector
(see user/shatov/ecdsa_fpga_model/test_vectors/)
Diffstat (limited to 'rtl/ecdsa256_wrapper.v')
| -rw-r--r-- | rtl/ecdsa256_wrapper.v | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/rtl/ecdsa256_wrapper.v b/rtl/ecdsa256_wrapper.v index 1684599..2b1d781 100644 --- a/rtl/ecdsa256_wrapper.v +++ b/rtl/ecdsa256_wrapper.v @@ -1,6 +1,6 @@ //====================================================================== // -// Copyright (c) 2016, NORDUnet A/S All rights reserved. +// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -31,17 +31,17 @@ //====================================================================== module ecdsa256_wrapper - ( - input wire clk, - input wire reset_n, +( + input wire clk, + input wire reset_n, - input wire cs, - input wire we, + input wire cs, + input wire we, - input wire [5: 0] address, - input wire [31: 0] write_data, - output wire [31: 0] read_data - ); + input wire [ 5:0] address, + input wire [31:0] write_data, + output wire [31:0] read_data +); // @@ -50,15 +50,15 @@ module ecdsa256_wrapper localparam ADDR_MSB_REGS = 1'b0; localparam ADDR_MSB_CORE = 1'b1; - wire [0:0] addr_msb = address[5]; - wire [4:0] addr_lsb = address[4:0]; + wire [0:0] addr_msb = address[5]; + wire [4:0] addr_lsb = address[4:0]; // // Output Mux // - wire [31: 0] read_data_regs; - wire [31: 0] read_data_core; + wire [31:0] read_data_regs; + wire [31:0] read_data_core; // @@ -80,45 +80,45 @@ module ecdsa256_wrapper localparam CORE_NAME0 = 32'h65636473; // "ecds" localparam CORE_NAME1 = 32'h61323536; // "a256" - localparam CORE_VERSION = 32'h302E3131; // "0.11" + localparam CORE_VERSION = 32'h302E3230; // "0.20" // // Registers // - reg reg_control; - reg [31:0] reg_dummy; + reg reg_control; + reg [31:0] reg_dummy; // // Wires // - wire reg_status; + wire reg_status; - // - // ECDSA256 - // - ecdsa256 ecdsa256_inst - ( - .clk (clk), - .rst_n (reset_n), + // + // ECDSA256 + // + ecdsa256_core_top ecdsa256_inst + ( + .clk (clk), + .rst_n (reset_n), - .next (reg_control), - .valid (reg_status), + .next (reg_control), + .valid (reg_status), - .bus_cs (cs && (addr_msb == ADDR_MSB_CORE)), - .bus_we (we), - .bus_addr (addr_lsb), - .bus_data_wr (write_data), - .bus_data_rd (read_data_core) - ); + .bus_cs (cs && (addr_msb == ADDR_MSB_CORE)), + .bus_we (we), + .bus_addr (addr_lsb), + .bus_data_wr (write_data), + .bus_data_rd (read_data_core) + ); // // Read Latch // - reg [31: 0] tmp_read_data; + reg [31:0] tmp_read_data; // @@ -139,7 +139,7 @@ module ecdsa256_wrapper case (addr_lsb) // ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT]; - ADDR_DUMMY: reg_dummy <= write_data; + ADDR_DUMMY: reg_dummy <= write_data; // endcase // @@ -154,7 +154,7 @@ module ecdsa256_wrapper ADDR_VERSION: tmp_read_data <= CORE_VERSION; ADDR_CONTROL: tmp_read_data <= {{30{1'b0}}, reg_control, 1'b0}; ADDR_STATUS: tmp_read_data <= {{30{1'b0}}, reg_status, 1'b1}; - ADDR_DUMMY: tmp_read_data <= reg_dummy; + ADDR_DUMMY: tmp_read_data <= reg_dummy; // default: tmp_read_data <= 32'h00000000; // |