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author | Rob Austein <sra@hactrn.net> | 2017-03-07 19:52:36 -0500 |
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committer | Rob Austein <sra@hactrn.net> | 2017-03-07 19:52:36 -0500 |
commit | 89f913c3aa2a6dad35630f3882a06b99e0978105 (patch) | |
tree | a8c05b11c926ad72f10a0c4b798ef4b46912e3bf /rtl/curve/rom/brom_p256_h_x.v | |
parent | 9fa6e368879d30835880b3bb0e87c8cf13dd9874 (diff) |
Promote to a repository in the core tree.
Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.
Code common between this core and the ecdsa384 core split out into a
separate library repository.
Minor cleanup (Windows-isms, indentation).
Diffstat (limited to 'rtl/curve/rom/brom_p256_h_x.v')
-rw-r--r-- | rtl/curve/rom/brom_p256_h_x.v | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/rtl/curve/rom/brom_p256_h_x.v b/rtl/curve/rom/brom_p256_h_x.v index 0b69f77..554d346 100644 --- a/rtl/curve/rom/brom_p256_h_x.v +++ b/rtl/curve/rom/brom_p256_h_x.v @@ -33,36 +33,36 @@ `timescale 1ns / 1ps module brom_p256_h_x - ( - input wire clk, - input wire [ 3-1:0] b_addr, - output wire [32-1:0] b_out - ); + ( + input wire clk, + input wire [ 3-1:0] b_addr, + output wire [32-1:0] b_out + ); // // Output Registers // - reg [31:0] bram_reg_b; + reg [31:0] bram_reg_b; assign b_out = bram_reg_b; // // Read-Only Port B - // - always @(posedge clk) - //
- case (b_addr)
- 3'b000: bram_reg_b <= 32'h4ece7ad0;
- 3'b001: bram_reg_b <= 32'h16bd8d74;
- 3'b010: bram_reg_b <= 32'ha42998be;
- 3'b011: bram_reg_b <= 32'h11f904fe;
- 3'b100: bram_reg_b <= 32'h38b77e1b;
- 3'b101: bram_reg_b <= 32'h0e863235;
- 3'b110: bram_reg_b <= 32'h3da77b71;
- 3'b111: bram_reg_b <= 32'h29d05c19;
- endcase + // + always @(posedge clk) + // + case (b_addr) + 3'b000: bram_reg_b <= 32'h4ece7ad0; + 3'b001: bram_reg_b <= 32'h16bd8d74; + 3'b010: bram_reg_b <= 32'ha42998be; + 3'b011: bram_reg_b <= 32'h11f904fe; + 3'b100: bram_reg_b <= 32'h38b77e1b; + 3'b101: bram_reg_b <= 32'h0e863235; + 3'b110: bram_reg_b <= 32'h3da77b71; + 3'b111: bram_reg_b <= 32'h29d05c19; + endcase endmodule |