| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-10-21 | Reworked testbench, clk_sys and clk_core can now have any ratio, not | Pavel V. Shatov (Meister) |
| 2019-10-21 | Further work: | Pavel V. Shatov (Meister) |
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) |
| 2019-10-03 | Added more micro-operations, also added "general worker" module. The worker i... | Pavel V. Shatov (Meister) |
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) |
| 2019-10-01 | Major rewrite (different core hierarchy, buses, wrappers, etc). | Pavel V. Shatov (Meister) |
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index : core/math/modexpng | |
| "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA | git repositories |
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