Redesigned the testbench. Core clock does not necessarily need to be twice

faster than the bus clock now. It can be the same, or say four times faster.

1 files changed, 79 insertions, 5 deletions

diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v
index 8c4e844..6b4ad3c 100644
--- a/rtl/modexpng_dsp_array_block.v
+++ b/rtl/modexpng_dsp_array_block.v
@@ -6,8 +6,9 @@ module modexpng_dsp_array_block
     a, b, p
 );
 
-    `include "modexpng_dsp48e1.vh"
     `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+    `include "modexpng_dsp_slice_primitive.vh"
 
     input                                            clk;
     
@@ -38,14 +39,87 @@ module modexpng_dsp_array_block
         ce_a2 <= ce_a1;
         ce_b1 <= ce_b0;
     end
-        
+    
+    ///
+    wire [46:0] p_debug_direct;
+    wire [17:0] casc_a_debug_direct;
+    wire [15:0] casc_b_debug_direct;
+    
+    wire [46:0] p_debug_cascade;
+
+    wire [46:0] p_ref_direct  = p[    0 +: MAC_W];
+    wire [46:0] p_ref_cascade = p[MAC_W +: MAC_W];
+    
+    modexpng_dsp_slice_wrapper_xilinx #
+    (
+        .AB_INPUT("DIRECT"),
+        .B_REG(2)
+    )
+    dsp_debug_direct
+    (
+        .clk            (clk),
+                
+        .ce_a1          (ce_a0),
+        .ce_b1          (ce_b0),
+        .ce_a2          (ce_a1),
+        .ce_b2          (ce_b1),
+        .ce_m           (ce_m),
+        .ce_p           (ce_p),
+        .ce_mode        (ce_mode),
+                
+        .a              (a[0 +: 18]),
+        .b              (b),
+        .p              (p_debug_direct),
+                
+        .inmode         ({DSP48E1_INMODE_W{1'b0}}),
+        .opmode         ({1'b0, mode_z[0], 1'b0, 2'b01, 2'b01}),
+        .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
+                
+        .casc_a_in      (WORD_EXT_ZERO),
+        .casc_b_in      (WORD_ZERO),
+                
+        .casc_a_out     (casc_a_debug_direct),
+        .casc_b_out     (casc_b_debug_direct)
+    );
+            
+    modexpng_dsp_slice_wrapper_xilinx #
+    (
+        .AB_INPUT("CASCADE"),
+        .B_REG(1)
+    )
+    dsp_debug_cascade
+    (
+        .clk            (clk),
+                
+        .ce_a1          (ce_a1),
+        .ce_b1          (1'b0),
+        .ce_a2          (ce_a2),
+        .ce_b2          (ce_b1),
+        .ce_m           (ce_m),
+        .ce_p           (ce_p),
+        .ce_mode        (ce_mode),
+                
+        .a              (a[0 +: 18]),
+        .b              (b),
+        .p              (p_debug_cascade),
+                
+        .inmode         ({DSP48E1_INMODE_W{1'b0}}),
+        .opmode         ({1'b0, mode_z[1], 1'b0, 2'b01, 2'b01}),
+        .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
+                
+        .casc_a_in      (casc_a_debug_direct),
+        .casc_b_in      (casc_b_debug_direct),
+                
+        .casc_a_out     (),
+        .casc_b_out     ()
+    );    
     
     genvar z;
     generate for (z=0; z<NUM_MULTS_HALF; z=z+1)
         //
         begin : gen_DSP48E1
             //        
-            modexpng_dsp_slice_wrapper #
+            `MODEXPNG_DSP_SLICE #
             (
                 .AB_INPUT("DIRECT"),
                 .B_REG(2)
@@ -77,7 +151,7 @@ module modexpng_dsp_array_block
                 .casc_b_out     (casc_b[z])
             );
             //
-            modexpng_dsp_slice_wrapper #
+            `MODEXPNG_DSP_SLICE #
             (
                 .AB_INPUT("CASCADE"),
                 .B_REG(1)
@@ -113,7 +187,7 @@ module modexpng_dsp_array_block
         //
     endgenerate
 
-    modexpng_dsp_slice_wrapper #
+    `MODEXPNG_DSP_SLICE #
     (
         .AB_INPUT("DIRECT"),
         .B_REG(2)