path: root/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v

//======================================================================
//
// Copyright: 2019, The Commons Conservancy Cryptech Project
// SPDX-License-Identifier: BSD-3-Clause
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the copyright holder nor the names of its
//   contributors may be used to endorse or promote products derived from
//   this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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//======================================================================

module modexpng_tdp_36k_x16_x32_wrapper_xilinx
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina, douta,
    
    enb, regceb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addra;
    input  [              BUS_DATA_W    -1:0] dina;
    output [              BUS_DATA_W    -1:0] douta;
    
    input                                     enb;
    input                                     regceb;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addrb;
    output [              WORD_W        -1:0] doutb;

    
    //
    // BRAM_TDP_MACRO
    //
    BRAM_TDP_MACRO #
    (
        .DEVICE                 ("7SERIES"),
        .BRAM_SIZE              ("36Kb"),

        .WRITE_WIDTH_A          (BUS_DATA_W),
        .READ_WIDTH_A           (BUS_DATA_W),

        .WRITE_WIDTH_B          (WORD_W),
        .READ_WIDTH_B           (WORD_W),

        .DOA_REG                (0),
        .DOB_REG                (1),

        .WRITE_MODE_A           ("READ_FIRST"),
        .WRITE_MODE_B           ("READ_FIRST"),

        .SRVAL_A                (36'h000000000),
        .SRVAL_B                (36'h000000000),

        .INIT_A                 (36'h000000000),
        .INIT_B                 (36'h000000000),
        
        .INIT_FILE              ("NONE"),
        .SIM_COLLISION_CHECK    ("NONE")
   )
   BRAM_TDP_MACRO_inst
   (
      .RSTA     (1'b0),
      .RSTB     (1'b0),

      .CLKA     (clk_bus),
      .ENA      (ena),
      .REGCEA   (1'b0),
      .WEA      ({4{wea}}),
      .ADDRA    (addra),
      .DIA      (dina),
      .DOA      (douta),

      .CLKB     (clk),
      .ENB      (enb),
      .REGCEB   (regceb),
      .WEB      ({2{1'b0}}),
      .ADDRB    (addrb),
      .DIB      ({WORD_W{1'b0}}),
      .DOB      (doutb)
   );
    
endmodule