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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-21 12:56:30 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-21 12:56:30 +0300
commit9eac252242c69e51a38a9a88c87b564dd40b6257 (patch)
treeab6653950a7f2a811598c73f15116fa5c009ec5c /rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
parent36339014ec3d3ad3bb4622392d5075d674e7dbeb (diff)
Entire CRT signature algorithm works by now.
Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled.
Diffstat (limited to 'rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v')
-rw-r--r--rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v88
1 files changed, 88 insertions, 0 deletions
diff --git a/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v b/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
new file mode 100644
index 0000000..81bcb85
--- /dev/null
+++ b/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
@@ -0,0 +1,88 @@
+module modexpng_tdp_36k_x16_x32_wrapper_xilinx
+(
+ clk, clk_bus,
+
+ ena, wea,
+ addra, dina, douta,
+
+ enb, regceb,
+ addrb, doutb
+);
+
+
+ //
+ // Headers
+ //
+ `include "modexpng_parameters.vh"
+
+
+ //
+ // Ports
+ //
+ input clk;
+ input clk_bus;
+
+ input ena;
+ input wea;
+ input [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addra;
+ input [ BUS_DATA_W -1:0] dina;
+ output [ BUS_DATA_W -1:0] douta;
+
+ input enb;
+ input regceb;
+ input [BANK_ADDR_W + OP_ADDR_W -1:0] addrb;
+ output [ WORD_W -1:0] doutb;
+
+
+ //
+ // BRAM_TDP_MACRO
+ //
+ BRAM_TDP_MACRO #
+ (
+ .DEVICE ("7SERIES"),
+ .BRAM_SIZE ("36Kb"),
+
+ .WRITE_WIDTH_A (BUS_DATA_W),
+ .READ_WIDTH_A (BUS_DATA_W),
+
+ .WRITE_WIDTH_B (WORD_W),
+ .READ_WIDTH_B (WORD_W),
+
+ .DOA_REG (0),
+ .DOB_REG (1),
+
+ .WRITE_MODE_A ("READ_FIRST"),
+ .WRITE_MODE_B ("READ_FIRST"),
+
+ .SRVAL_A (36'h000000000),
+ .SRVAL_B (36'h000000000),
+
+ .INIT_A (36'h000000000),
+ .INIT_B (36'h000000000),
+
+ .INIT_FILE ("NONE"),
+ .SIM_COLLISION_CHECK ("NONE")
+ )
+ BRAM_TDP_MACRO_inst
+ (
+ .RSTA (1'b0),
+ .RSTB (1'b0),
+
+ .CLKA (clk_bus),
+ .ENA (ena),
+ .REGCEA (1'b0),
+ .WEA ({4{wea}}),
+ .ADDRA (addra),
+ .DIA (dina),
+ .DOA (douta),
+
+ .CLKB (clk),
+ .ENB (enb),
+ .REGCEB (regceb),
+ .WEB ({2{1'b0}}),
+ .ADDRB (addrb),
+ .DIB ({WORD_W{1'b0}}),
+ .DOB (doutb)
+ );
+
+endmodule