Age | Commit message (Expand) | Author |
---|---|---|
2017-07-23 | Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ... | Pavel V. Shatov (Meister) |
2017-07-10 | * made separate file for low-level settings | Pavel V. Shatov (Meister) |
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index : core/math/modexpa7 | |
Modular exponentiation using the Artix-7 FPGA | git repositories |
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Age | Commit message (Expand) | Author |
---|---|---|
2017-07-23 | Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ... | Pavel V. Shatov (Meister) |
2017-07-10 | * made separate file for low-level settings | Pavel V. Shatov (Meister) |