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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-25 01:21:28 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-25 01:21:28 +0300
commitbd6c4a9b916cd36890ebec72fae50555dfe6e7ba (patch)
tree9ab163d65bbd0c90f016abe4325685fb463d0b5c /src/tb
parentc4326507c85196bd30adb4d20ce07448a8306066 (diff)
Trying to fix the bug during calculation of SN in systolic multiplier.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_exponentiator.v2
-rw-r--r--src/tb/tb_systolic_multiplier.v6
-rw-r--r--src/tb/tb_wrapper.v44
3 files changed, 48 insertions, 4 deletions
diff --git a/src/tb/tb_exponentiator.v b/src/tb/tb_exponentiator.v
index c854e65..c9a9f7e 100644
--- a/src/tb/tb_exponentiator.v
+++ b/src/tb/tb_exponentiator.v
@@ -207,7 +207,7 @@ module tb_exponentiator;
rst_n = 1'b1;
#100;
- test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
+ //test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);
end
diff --git a/src/tb/tb_systolic_multiplier.v b/src/tb/tb_systolic_multiplier.v
index 33d1e01..61dc6f3 100644
--- a/src/tb/tb_systolic_multiplier.v
+++ b/src/tb/tb_systolic_multiplier.v
@@ -57,7 +57,7 @@ module tb_systolic_multiplier;
//
// Model Settings
//
- localparam NUM_ROUNDS = 10;
+ localparam NUM_ROUNDS = 43;
//
@@ -152,7 +152,7 @@ module tb_systolic_multiplier;
modexpa7_systolic_multiplier #
(
.OPERAND_ADDR_WIDTH (4), // 32 * (2**4) = 512-bit operands
- .SYSTOLIC_ARRAY_POWER (2) // 2 ** 2 = 4-tap array
+ .SYSTOLIC_ARRAY_POWER (3) // 2 ** 2 = 4-tap array
)
uut
(
@@ -193,7 +193,7 @@ module tb_systolic_multiplier;
#100;
test_systolic_multiplier_384(M_384, N_384, N_COEFF_384, FACTOR_384, COEFF_384);
- test_systolic_multiplier_512(M_512, N_512, N_COEFF_512, FACTOR_512, COEFF_512);
+ //test_systolic_multiplier_512(M_512, N_512, N_COEFF_512, FACTOR_512, COEFF_512);
end
diff --git a/src/tb/tb_wrapper.v b/src/tb/tb_wrapper.v
new file mode 100644
index 0000000..bd8dbf1
--- /dev/null
+++ b/src/tb/tb_wrapper.v
@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps
+
+module tb_wrapper;
+
+ // Inputs
+ reg clk;
+ reg rst_n;
+ reg cs;
+ reg we;
+ reg [7:0] address;
+ reg [31:0] write_data;
+
+ // Outputs
+ wire [31:0] read_data;
+
+ // Instantiate the Unit Under Test (UUT)
+ modexpa7_wrapper uut (
+ .clk(clk),
+ .rst_n(rst_n),
+ .cs(cs),
+ .we(we),
+ .address(address),
+ .write_data(write_data),
+ .read_data(read_data)
+ );
+
+ initial begin
+ // Initialize Inputs
+ clk = 0;
+ rst_n = 0;
+ cs = 0;
+ we = 0;
+ address = 0;
+ write_data = 0;
+
+ // Wait 100 ns for global reset to finish
+ #100;
+
+ // Add stimulus here
+
+ end
+
+endmodule
+