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-rw-r--r--src/tb/tb_wrapper.v44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/tb/tb_wrapper.v b/src/tb/tb_wrapper.v
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+`timescale 1ns / 1ps
+
+module tb_wrapper;
+
+ // Inputs
+ reg clk;
+ reg rst_n;
+ reg cs;
+ reg we;
+ reg [7:0] address;
+ reg [31:0] write_data;
+
+ // Outputs
+ wire [31:0] read_data;
+
+ // Instantiate the Unit Under Test (UUT)
+ modexpa7_wrapper uut (
+ .clk(clk),
+ .rst_n(rst_n),
+ .cs(cs),
+ .we(we),
+ .address(address),
+ .write_data(write_data),
+ .read_data(read_data)
+ );
+
+ initial begin
+ // Initialize Inputs
+ clk = 0;
+ rst_n = 0;
+ cs = 0;
+ we = 0;
+ address = 0;
+ write_data = 0;
+
+ // Wait 100 ns for global reset to finish
+ #100;
+
+ // Add stimulus here
+
+ end
+
+endmodule
+