diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/modexp.v | 171 | ||||
| -rw-r--r-- | src/tb/tb_modexp.v | 3 |
2 files changed, 127 insertions, 47 deletions
diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v index e8f8a1d..8e8d9b1 100644 --- a/src/rtl/modexp.v +++ b/src/rtl/modexp.v @@ -71,21 +71,23 @@ module modexp( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam GENERAL_PREFIX = 4'h0; - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; + localparam GENERAL_PREFIX = 4'h0; + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; - localparam ADDR_CTRL = 8'h08; - localparam CTRL_INIT_BIT = 0; - localparam CTRL_NEXT_BIT = 1; + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; - localparam ADDR_STATUS = 8'h09; - localparam STATUS_READY_BIT = 0; + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; - localparam ADDR_MODULUS_LENGTH = 8'h20; - localparam ADDR_EXPONENT_LENGTH = 8'h21; - localparam ADDR_LENGTH = 8'h22; // Should be deprecated. + localparam ADDR_CYCLES_HIGH = 8'h10; + localparam ADDR_CYCLES_LOW = 8'h11; + + localparam ADDR_MODULUS_LENGTH = 8'h20; + localparam ADDR_EXPONENT_LENGTH = 8'h21; localparam ADDR_MODULUS_PTR_RST = 8'h30; localparam ADDR_MODULUS_DATA = 8'h31; @@ -99,8 +101,8 @@ module modexp( localparam ADDR_RESULT_PTR_RST = 8'h60; localparam ADDR_RESULT_DATA = 8'h61; - localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits. - localparam DEFAULT_EXPLENGTH = 8'h80; + localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits. + localparam DEFAULT_EXPLENGTH = 8'h80; localparam MONTPROD_SELECT_ONE_NR = 3'h0; localparam MONTPROD_SELECT_X_NR = 3'h1; @@ -187,6 +189,18 @@ module modexp( reg exponation_mode_new; reg exponation_mode_we; + reg [31 : 0] cycle_ctr_low_reg; + reg [31 : 0] cycle_ctr_low_new; + reg cycle_ctr_low_we; + reg [31 : 0] cycle_ctr_high_reg; + reg [31 : 0] cycle_ctr_high_new; + reg cycle_ctr_high_we; + reg cycle_ctr_state_reg; + reg cycle_ctr_state_new; + reg cycle_ctr_state_we; + reg cycle_ctr_start; + reg cycle_ctr_stop; + //---------------------------------------------------------------- // Wires. @@ -219,7 +233,6 @@ module modexp( reg p_mem_we; reg [31 : 0] tmp_read_data; - //reg tmp_error; reg montprod_calc; wire montprod_ready; @@ -238,17 +251,17 @@ module modexp( wire [31 : 0] montprod_result_data; wire montprod_result_we; - reg residue_calculate; - wire residue_ready; - reg [14 : 0] residue_nn; - reg [07 : 0] residue_length; - wire [07 : 0] residue_opa_rd_addr; - wire [31 : 0] residue_opa_rd_data; - wire [07 : 0] residue_opa_wr_addr; - wire [31 : 0] residue_opa_wr_data; - wire residue_opa_wr_we; - wire [07 : 0] residue_opm_addr; - reg [31 : 0] residue_opm_data; + reg residue_calculate; + wire residue_ready; + reg [14 : 0] residue_nn; + reg [07 : 0] residue_length; + wire [07 : 0] residue_opa_rd_addr; + wire [31 : 0] residue_opa_rd_data; + wire [07 : 0] residue_opa_wr_addr; + wire [31 : 0] residue_opa_wr_data; + wire residue_opa_wr_we; + wire [07 : 0] residue_opm_addr; + reg [31 : 0] residue_opm_data; reg [07 : 0] residue_mem_montprod_read_addr; wire [31 : 0] residue_mem_montprod_read_data; @@ -423,6 +436,9 @@ module modexp( ei_reg <= 1'b0; residue_valid_reg <= 1'b0; exponation_mode_reg <= EXPONATION_MODE_SECRET_SECURE; + cycle_ctr_low_reg <= 32'h00000000; + cycle_ctr_high_reg <= 32'h00000000; + cycle_ctr_state_reg <= 1'b0; end else begin @@ -431,12 +447,14 @@ module modexp( residue_valid_reg <= residue_valid_new; if (exponent_length_we) - exponent_length_reg <= exponent_length_new; + begin + exponent_length_reg <= exponent_length_new; + end if (modulus_length_we) begin modulus_length_reg <= modulus_length_new; - length_m1_reg <= length_m1_new; + length_m1_reg <= length_m1_new; end if (start_we) @@ -451,9 +469,6 @@ module modexp( if (montprod_dest_we) montprod_dest_reg <= montprod_dest_new; - if (modexp_ctrl_we) - modexp_ctrl_reg <= modexp_ctrl_new; - if (loop_counter_we) loop_counter_reg <= loop_counter_new; @@ -462,6 +477,18 @@ module modexp( if (exponation_mode_we) exponation_mode_reg <= exponation_mode_new; + + if (cycle_ctr_low_we) + cycle_ctr_low_reg <= cycle_ctr_low_new; + + if (cycle_ctr_high_we) + cycle_ctr_high_reg <= cycle_ctr_high_new; + + if (cycle_ctr_state_we) + cycle_ctr_state_reg <= cycle_ctr_state_new; + + if (modexp_ctrl_we) + modexp_ctrl_reg <= modexp_ctrl_new; end end // reg_update @@ -599,6 +626,12 @@ module modexp( ADDR_STATUS: tmp_read_data = {31'h00000000, ready_reg}; + ADDR_CYCLES_HIGH: + tmp_read_data = cycle_ctr_high_reg; + + ADDR_CYCLES_LOW: + tmp_read_data = cycle_ctr_low_reg; + ADDR_MODULUS_LENGTH: tmp_read_data = {24'h000000, modulus_length_reg}; @@ -646,6 +679,50 @@ module modexp( //---------------------------------------------------------------- + // cycle_ctr + // + // Implementation of the cycle counter + //---------------------------------------------------------------- + always @* + begin : cycle_ctr + cycle_ctr_low_new = 32'h00000000; + cycle_ctr_low_we = 1'b0; + cycle_ctr_high_new = 32'h00000000; + cycle_ctr_high_we = 1'b0; + cycle_ctr_state_new = 1'b0; + cycle_ctr_state_we = 1'b0; + + if (cycle_ctr_start) + begin + cycle_ctr_low_new = 32'h00000000; + cycle_ctr_low_we = 1'b1; + cycle_ctr_high_new = 32'h00000000; + cycle_ctr_high_we = 1'b1; + cycle_ctr_state_new = 1'b1; + cycle_ctr_state_we = 1'b1; + end + + if (cycle_ctr_stop) + begin + cycle_ctr_state_new = 1'b0; + cycle_ctr_state_we = 1'b1; + end + + if (cycle_ctr_state_reg) + begin + cycle_ctr_low_new = cycle_ctr_low_reg + 1'b1; + cycle_ctr_low_we = 1'b1; + + if (cycle_ctr_low_new == 32'h00000000) + begin + cycle_ctr_high_new = cycle_ctr_high_reg + 1'b1; + cycle_ctr_high_we = 1'b1; + end + end + end // cycle_ctr + + + //---------------------------------------------------------------- // one // // generates the big integer one ( 00... 01 ) @@ -722,38 +799,38 @@ module modexp( case (montprod_select_reg) MONTPROD_SELECT_ONE_NR: begin - montprod_opa_data = one_reg; - montprod_opb_data = residue_mem_montprod_read_data; + montprod_opa_data = one_reg; + montprod_opb_data = residue_mem_montprod_read_data; end MONTPROD_SELECT_X_NR: begin - montprod_opa_data = message_mem_int_rd_data; - montprod_opb_data = residue_mem_montprod_read_data; + montprod_opa_data = message_mem_int_rd_data; + montprod_opb_data = residue_mem_montprod_read_data; end MONTPROD_SELECT_Z_P: begin - montprod_opa_data = result_mem_int_rd_data; - montprod_opb_data = p_mem_rd1_data; + montprod_opa_data = result_mem_int_rd_data; + montprod_opb_data = p_mem_rd1_data; end MONTPROD_SELECT_P_P: begin - montprod_opa_data = p_mem_rd0_data; - montprod_opb_data = p_mem_rd1_data; + montprod_opa_data = p_mem_rd0_data; + montprod_opb_data = p_mem_rd1_data; end MONTPROD_SELECT_Z_ONE: begin - montprod_opa_data = result_mem_int_rd_data; - montprod_opb_data = b_one_reg; + montprod_opa_data = result_mem_int_rd_data; + montprod_opb_data = b_one_reg; end default: begin - montprod_opa_data = 32'h00000000; - montprod_opb_data = 32'h00000000; + montprod_opa_data = 32'h00000000; + montprod_opb_data = 32'h00000000; end endcase // case (montprod_selcect_reg) end @@ -866,6 +943,8 @@ module modexp( modexp_ctrl_new = CTRL_IDLE; modexp_ctrl_we = 1'b0; clear_start = 1'b0; + cycle_ctr_start = 1'b0; + cycle_ctr_stop = 1'b0; residue_calculate = 1'b0; @@ -878,8 +957,8 @@ module modexp( begin ready_new = 1'b0; ready_we = 1'b1; - modexp_ctrl_new = CTRL_DONE; - modexp_ctrl_we = 1'b1; + clear_start = 1'b1; + cycle_ctr_start = 1'b1; if (residue_valid_reg) begin @@ -1008,7 +1087,7 @@ module modexp( CTRL_DONE: begin - clear_start = 1'b1; + cycle_ctr_stop = 1'b1; ready_new = 1'b1; ready_we = 1'b1; modexp_ctrl_new = CTRL_IDLE; diff --git a/src/tb/tb_modexp.v b/src/tb/tb_modexp.v index 6f9ea19..4b3029e 100644 --- a/src/tb/tb_modexp.v +++ b/src/tb/tb_modexp.v @@ -204,7 +204,8 @@ module tb_modexp(); #(CLK_PERIOD); if (DISPLAY_TEST_CYCLES) - $display("*** Number of cycles performed during test: 0x%016x", test_cycle_ctr); + $display("*** Number of cycles performed during test: 0x%016x", + {dut.cycle_ctr_high_reg, dut.cycle_ctr_low_reg}); end endtask // stop_test_cycle_ctr() |