Fixed incorrect compile time expression for sizing the memory.

1 files changed, 1 insertions, 1 deletions

diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v
index 6a28cc2..6856e0a 100644
--- a/src/rtl/blockmem1r1w.v
+++ b/src/rtl/blockmem1r1w.v
@@ -54,7 +54,7 @@ module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
                     input wire  [(OPW - 1) : 0] write_data
                    );
 
-  reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
   reg [(OPW - 1) : 0] tmp_read_data;
 
   assign read_data = tmp_read_data;