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//======================================================================
//
// Copyright (c) 2017, NORDUnet A/S All rights reserved.
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//======================================================================

`timescale 1ns / 1ps

module bram_1rw_readfirst
  #(parameter MEM_WIDTH            = 32,
    parameter MEM_ADDR_BITS        = 8)
   (
    input wire                     clk,

    input wire [MEM_ADDR_BITS-1:0] a_addr,
    input wire                     a_wr,
    input wire [MEM_WIDTH-1:0]     a_in,
    output wire [MEM_WIDTH-1:0]    a_out
    );


   //
   // BRAM
   //
   (* RAM_STYLE="BLOCK" *)
   reg [MEM_WIDTH-1:0]             bram[0:(2**MEM_ADDR_BITS)-1];
	
	
   //
   // Output Register
   //
   reg [MEM_WIDTH-1:0]             bram_reg_a;

   assign a_out = bram_reg_a;


   //
   // Read-Write Port A
   //
   always @(posedge clk) begin
      //
      bram_reg_a <= bram[a_addr];
      //
      if (a_wr) bram[a_addr] <= a_in;
      //
   end


endmodule