| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-04-03 | Connected all dangling dut ports in the core testbench. Fixed RTL code that c... | Joachim Strömbergson |
| 2018-04-03 | Non functional cleanups: (1) Changed name of round counter to show what is us... | Joachim Strömbergson |
| 2018-04-03 | Added second round state to allow for one cycle propagation of t1 in a future... | Joachim Strömbergson |
| 2015-12-13 | whack copyrights | Paul Selkirk |
| 2015-07-18 | Adding logic to write state restore data to the state registers. | Joachim Strömbergson |
| 2015-07-18 | Adding ports in the core to do state restore. Added wires in the top to conne... | Joachim Strömbergson |
| 2014-11-20 | Adding work factor processing functionality. | Joachim Strömbergson |
| 2014-11-06 | Fixes of nits in #8 found with the verilator linter. | Joachim Strömbergson |
| 2014-09-11 | Changed to asynch reset. | Joachim Strömbergson |
| 2014-04-05 | Adding source RTL files for the sha512 core. | Joachim Strömbergson |
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index : core/hash/sha512 | |
| Verilog implementation of the SHA-512 hash function | git repositories |
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