Changed to asynch reset.

1 files changed, 2 insertions, 2 deletions

diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index c3a2de6..73bbcee 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -198,10 +198,10 @@ module sha512_core(
   //----------------------------------------------------------------
   // reg_update
   // Update functionality for all registers in the core.
-  // All registers are positive edge triggered with synchronous
+  // All registers are positive edge triggered with asynchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
       if (!reset_n)
         begin