From 6f28e4f30356e8e07941b9fe87a0debc26f89f8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 11 Sep 2014 17:42:34 +0200 Subject: Changed to asynch reset. --- src/rtl/sha512_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/rtl/sha512_core.v') diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index c3a2de6..73bbcee 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -198,10 +198,10 @@ module sha512_core( //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous + // All registers are positive edge triggered with asynchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin -- cgit v1.2.3