core/hash/sha512 - Verilog implementation of the SHA-512 hash function

Branch	Commit message	Author	Age
clock_speed	Added reg on output from w_mem to split long path. Adjusted when w_next is se...	Joachim Strömbergson	6 years
master	Merged clock speed optimization work.	Joachim Strömbergson	6 years


Age	Commit message	Author
2018-12-04	Added reg on output from w_mem to split long path. Adjusted when w_next is se...clock_speed	Joachim Strömbergson
2018-04-25	Added pipeline cycle for t1 and t2 calculations. Updated and cleaned up the W...	Joachim Strömbergson
2018-04-24	Removed redundant code by fusing expression.	Joachim Strömbergson
2018-04-24	Fixing reg update signals. Fixing names.	Joachim Strömbergson
2018-04-23	Correcting name for t1 and t2 update vectors. Cleaned up constants.	Joachim Strömbergson
2018-04-23	Minor cleanup.	Joachim Strömbergson
2018-04-06	Updated state display. Added cycle count display.	Joachim Strömbergson
2018-04-06	Added registers for t1 and t2. Updated tb to look at update vectors.	Joachim Strömbergson
2018-04-06	Minor cleanup of mask definition to make it easier to understand.	Joachim Strömbergson
2018-04-06	Added support for dumping T2 inputs and calculations.	Joachim Strömbergson
[...]

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https://git.cryptech.is/core/hash/sha512