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authorPaul Selkirk <paul@psgd.org>2021-06-02 16:11:17 -0400
committerPaul Selkirk <paul@psgd.org>2021-06-02 16:11:17 -0400
commit4c32ceb2f2df74de8996b9a76667643feb18f4e6 (patch)
treebb7019d8ee4736d15e03c85a73ad43c8a2bce0f2 /src
parent9c5acbbcd7928a2958d370923d9cc0276037f1aa (diff)
Change reads from clocked to unclocked to match read timing of other cores.
Diffstat (limited to 'src')
-rw-r--r--src/rtl/sha3.v8
-rw-r--r--src/rtl/sha3_wrapper.v58
2 files changed, 30 insertions, 36 deletions
diff --git a/src/rtl/sha3.v b/src/rtl/sha3.v
index b01d50c..ee29ba6 100644
--- a/src/rtl/sha3.v
+++ b/src/rtl/sha3.v
@@ -98,11 +98,11 @@ module sha3( input wire clk,
/* the lowest address bit determines what part of 64-bit word to return */
- always @(posedge clk)
+ always @*
//
- dout <= addr[8] ?
- (~addr[2] ? st [addr[7:3]][31:0] : st [addr[7:3]][63:32]) :
- (~addr[2] ? blk[addr[7:3]][31:0] : blk[addr[7:3]][63:32]) ;
+ dout = addr[8] ?
+ (~addr[2] ? st [addr[7:3]][31:0] : st [addr[7:3]][63:32]) :
+ (~addr[2] ? blk[addr[7:3]][31:0] : blk[addr[7:3]][63:32]) ;
always @* begin
diff --git a/src/rtl/sha3_wrapper.v b/src/rtl/sha3_wrapper.v
index c19f64f..f3dc554 100644
--- a/src/rtl/sha3_wrapper.v
+++ b/src/rtl/sha3_wrapper.v
@@ -149,46 +149,40 @@ module sha3_wrapper
//
reg_control <= 2'b00;
//
- end else if (cs && (addr_msb == ADDR_MSB_REGS)) begin
+ end else if (cs && we && (addr_msb == ADDR_MSB_REGS)) begin
//
- if (we) begin
- //
- // Write Handler
- //
- case (addr_lsb)
- //
- ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT:CONTROL_INIT_BIT];
- //
- endcase
- //
- end else begin
- //
- // Read Handler
- //
- case (address)
- //
- ADDR_NAME0: tmp_read_data <= CORE_NAME0;
- ADDR_NAME1: tmp_read_data <= CORE_NAME1;
- ADDR_VERSION: tmp_read_data <= CORE_VERSION;
- ADDR_CONTROL: tmp_read_data <= {{30{1'b0}}, reg_control};
- ADDR_STATUS: tmp_read_data <= {{30{1'b0}}, reg_status_valid, 1'b1};
- //
- default: tmp_read_data <= 32'h00000000;
- //
- endcase
- //
- end
+ // Write Handler
+ //
+ case (addr_lsb)
+ //
+ ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT:CONTROL_INIT_BIT];
+ //
+ endcase
//
end
+ always @*
+ if (cs && !we && (addr_msb == ADDR_MSB_REGS))
+ //
+ // Read Handler
+ //
+ case (address)
+ //
+ ADDR_NAME0: tmp_read_data = CORE_NAME0;
+ ADDR_NAME1: tmp_read_data = CORE_NAME1;
+ ADDR_VERSION: tmp_read_data = CORE_VERSION;
+ ADDR_CONTROL: tmp_read_data = {{30{1'b0}}, reg_control};
+ ADDR_STATUS: tmp_read_data = {{30{1'b0}}, reg_status_valid, 1'b1};
+ //
+ default: tmp_read_data = 32'h00000000;
+ //
+ endcase
+
//
// Register / Core Memory Selector
//
- reg addr_msb_last;
- always @(posedge clk) addr_msb_last <= addr_msb;
-
- assign read_data = (addr_msb_last == ADDR_MSB_REGS) ? tmp_read_data : read_data_core;
+ assign read_data = (addr_msb == ADDR_MSB_REGS) ? tmp_read_data : read_data_core;
endmodule