aboutsummaryrefslogtreecommitdiff
path: root/src/rtl/sha3_wrapper.v
blob: f3dc5548a3a453b4d96436987b552e998c93d930 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
//======================================================================
//
// Copyright (c) 2017, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module sha3_wrapper
  (
   input wire          clk,
   input wire          rst_n,

   input wire          cs,
   input wire          we,

   input wire [7: 0]   address,
   input wire [31: 0]  write_data,
   output wire [31: 0] read_data
   );


   //
   // Address Decoder
   //
   localparam ADDR_MSB_REGS = 1'b0;
   localparam ADDR_MSB_CORE = 1'b1;

   wire [0:0] addr_msb = address[7];
   wire [6:0] addr_lsb = address[6:0];


   //
   // Output Mux
   //
   wire [31: 0] read_data_regs;
   wire [31: 0] read_data_core;


   //
   // Registers
   //
   localparam ADDR_NAME0        = 5'h00;
   localparam ADDR_NAME1        = 5'h01;
   localparam ADDR_VERSION      = 5'h02;

   localparam ADDR_CONTROL      = 5'h08;               // {next, init}
   localparam ADDR_STATUS       = 5'h09;               // {valid, ready}

   localparam CONTROL_INIT_BIT  = 0;
   localparam CONTROL_NEXT_BIT  = 1;

// localparam STATUS_READY_BIT  = 0; -- hardcoded to always read 1
   localparam STATUS_VALID_BIT  = 1;

   localparam CORE_NAME0        = 32'h73686133; // "sha3"
   localparam CORE_NAME1        = 32'h20202020; // "    " [four spaces]
   localparam CORE_VERSION      = 32'h302E3130; // "0.10"


   //
   // Registers
   //
   reg [ 1:0] reg_control;
   reg [ 1:0] reg_control_prev;


   //
   // Flags
   //
   wire       reg_control_init_posedge =
              reg_control[CONTROL_INIT_BIT] & ~reg_control_prev[CONTROL_INIT_BIT];

   wire       reg_control_next_posedge =
              reg_control[CONTROL_NEXT_BIT] & ~reg_control_prev[CONTROL_NEXT_BIT];


   //
   // Wires
   //
   wire reg_status_valid;


   //
   // SHA-3
   //
   sha3 sha3_inst
     (
      .clk                      (clk),
      .nreset                   (rst_n),

      .init                     (reg_control_init_posedge),
      .next                     (reg_control_next_posedge),

      .ready                    (reg_status_valid),

      .w                        (we && (addr_msb == ADDR_MSB_CORE)),
      .addr                     (addr_lsb),
      .din                      (write_data),
      .dout                     (read_data_core)
      );


   //
   // Read Latch
   //
   reg [31: 0]         tmp_read_data;


   //
   // Control Register Delay Block
   //
   always @(posedge clk)
     //
     if (!rst_n)        reg_control_prev <= 2'b00;
          else          reg_control_prev <= reg_control;


   //
   // Read/Write Interface
   //
   always @(posedge clk)
     //
     if (!rst_n) begin
        //
        reg_control <= 2'b00;
        //
     end else if (cs && we && (addr_msb == ADDR_MSB_REGS)) begin
        //
        // Write Handler
        //
        case (addr_lsb)
          //
          ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT:CONTROL_INIT_BIT];
          //
        endcase
        //
     end

   always @*
     if (cs && !we && (addr_msb == ADDR_MSB_REGS))
       //
       // Read Handler
       //
       case (address)
         //
         ADDR_NAME0:        tmp_read_data = CORE_NAME0;
         ADDR_NAME1:        tmp_read_data = CORE_NAME1;
         ADDR_VERSION:      tmp_read_data = CORE_VERSION;
         ADDR_CONTROL:      tmp_read_data = {{30{1'b0}}, reg_control};
         ADDR_STATUS:       tmp_read_data = {{30{1'b0}}, reg_status_valid, 1'b1};
         //
         default:           tmp_read_data = 32'h00000000;
         //
       endcase


   //
   // Register / Core Memory Selector
   //
   assign read_data = (addr_msb == ADDR_MSB_REGS) ? tmp_read_data : read_data_core;


endmodule