Age | Commit message (Collapse) | Author | |
---|---|---|---|
2018-08-28 | Connected the pipeline regs for t1 and t2 in the stat update logic. Verified ↵ | Joachim Strömbergson | |
functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1. | |||
2018-04-27 | Removed FSM and cleaned up code in W mem. Cleaned up testbenches to silence ↵ | Joachim Strömbergson | |
warnings. | |||
2016-05-31 | Adding functionality to support both SHA224 and SHA256 digest modes. Note: ↵ | Joachim Strömbergson | |
This update changes the ADDR_CTRL API register since it adds a mode bit. The version major number has been bumped to reflect this API change. The top level testbench contains tests for SHA224 as well as old tests for SHA256. The core level tb still only tests SHA256. | |||
2015-12-13 | whack copyrights | Paul Selkirk | |
2015-07-17 | Fixed state restore testcase in core testbench. Fixed the double block test ↵ | Joachim Strömbergson | |
case to really test the core. Added data valid task. | |||
2015-07-16 | Adding a task to dump the H state. | Joachim Strömbergson | |
2015-07-16 | Adding test case for state restore. | Joachim Strömbergson | |
2014-03-16 | Adding self resetting init and next flags. Updating TBs to not reset the ↵ | Joachim Strömbergson | |
flags. Fixing clock parameter naming. | |||
2014-02-22 | Updated testbenches to the new sliding window W-mem. | Joachim Strömbergson | |
2014-02-19 | Adding a testbench for the SHA256 core. | Joachim Strömbergson | |