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@@ -74,6 +74,19 @@ Implementation results using Altera Quartus-II 13.1.
 - 66 cycles latency
 
 
+### Xilinx Artix-7 FPGAs ###
+Implementation results using Xilinx ISE 14.7
+This implementation includes pipeline regsisters.
+
+- xc7a200t-1fbg484
+- 2229 Slice LUTs
+- 775 Slices
+- 1935 registers
+- 101 MHz
+- 130 cycles latency
+
+
+
 ## TODO ##
 - Extensive verification in physical device.
 - Complete documentation.