Connected the pipeline regs for t1 and t2 in the stat update logic. Verified functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1.

1 files changed, 13 insertions, 0 deletions

diff --git a/README.md b/README.md
index 79f17f5..1790058 100644
--- a/README.md
+++ b/README.md
@@ -74,6 +74,19 @@ Implementation results using Altera Quartus-II 13.1.
 - 66 cycles latency
 
 
+### Xilinx Artix-7 FPGAs ###
+Implementation results using Xilinx ISE 14.7
+This implementation includes pipeline regsisters.
+
+- xc7a200t-1fbg484
+- 2229 Slice LUTs
+- 775 Slices
+- 1935 registers
+- 101 MHz
+- 130 cycles latency
+
+
+
 ## TODO ##
 - Extensive verification in physical device.
 - Complete documentation.