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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-08-28 12:44:40 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-08-28 12:44:40 +0200
commit0e7de630d80ad112bbb430434b6a5830d357d3d6 (patch)
tree703c7531a03b42bbe68a78f1c2299df82a99f08d /src/tb/tb_sha256_core.v
parentd2d5cb5efef2b77b728b97280209121020189010 (diff)
Added pipeline register and stall cycle in the FSM to accomodate the pipeline. Registers not yet used in the design. Cleaned up constants to silence lint.
Diffstat (limited to 'src/tb/tb_sha256_core.v')
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