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author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-11-07 11:56:50 +0100 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-11-07 11:56:50 +0100 |
commit | bbfa764f84bd2f76a011b53eaa4cd5f2178577c4 (patch) | |
tree | a7c9f802d978963152b68829145b0b40b3150ba8 /src/rtl/sha256_core.v | |
parent | c4cd88c7b8375b4696a6533ed419ddee3156ba9b (diff) |
Changed to asynch reset.
Diffstat (limited to 'src/rtl/sha256_core.v')
-rw-r--r-- | src/rtl/sha256_core.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v index d4330d9..a88a359 100644 --- a/src/rtl/sha256_core.v +++ b/src/rtl/sha256_core.v @@ -183,10 +183,10 @@ module sha256_core( //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous - // active low reset. All registers have write enable. + // All registers are positive edge triggered with + // asynchronous active low reset. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin |