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author | Joachim StroĢmbergson <joachim@secworks.se> | 2016-05-31 13:30:12 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2016-05-31 13:30:12 +0200 |
commit | 0e90cfa1f076b8660610dfd3930ef1b37a1fb41e (patch) | |
tree | 9b6b5bc380394845847ab4930b8fa36422b0f6aa /src/model | |
parent | c96748481784c451b80e2ba84a504d04e509f26d (diff) |
Fixed long constants and instead rely on zero extend in Verilog.
Diffstat (limited to 'src/model')
0 files changed, 0 insertions, 0 deletions