aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorJoachim StroĢˆmbergson <joachim@secworks.se>2016-05-31 13:30:12 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2016-05-31 13:30:12 +0200
commit0e90cfa1f076b8660610dfd3930ef1b37a1fb41e (patch)
tree9b6b5bc380394845847ab4930b8fa36422b0f6aa /src
parentc96748481784c451b80e2ba84a504d04e509f26d (diff)
Fixed long constants and instead rely on zero extend in Verilog.
Diffstat (limited to 'src')
-rw-r--r--src/rtl/sha256.v34
1 files changed, 17 insertions, 17 deletions
diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index 7e1035f..1f9e75e 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -236,24 +236,24 @@ module sha256(
init_reg <= 0;
next_reg <= 0;
ready_reg <= 0;
- digest_reg <= 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ digest_reg <= 256'h0;
digest_valid_reg <= 0;
- block0_reg <= 32'h00000000;
- block1_reg <= 32'h00000000;
- block2_reg <= 32'h00000000;
- block3_reg <= 32'h00000000;
- block4_reg <= 32'h00000000;
- block5_reg <= 32'h00000000;
- block6_reg <= 32'h00000000;
- block7_reg <= 32'h00000000;
- block8_reg <= 32'h00000000;
- block9_reg <= 32'h00000000;
- block10_reg <= 32'h00000000;
- block11_reg <= 32'h00000000;
- block12_reg <= 32'h00000000;
- block13_reg <= 32'h00000000;
- block14_reg <= 32'h00000000;
- block15_reg <= 32'h00000000;
+ block0_reg <= 32'h0;
+ block1_reg <= 32'h0;
+ block2_reg <= 32'h0;
+ block3_reg <= 32'h0;
+ block4_reg <= 32'h0;
+ block5_reg <= 32'h0;
+ block6_reg <= 32'h0;
+ block7_reg <= 32'h0;
+ block8_reg <= 32'h0;
+ block9_reg <= 32'h0;
+ block10_reg <= 32'h0;
+ block11_reg <= 32'h0;
+ block12_reg <= 32'h0;
+ block13_reg <= 32'h0;
+ block14_reg <= 32'h0;
+ block15_reg <= 32'h0;
end
else
begin