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2018-10-16Added width definition to reset values as part of checking that all ↵Joachim Strömbergson
registers are properly reset.
2018-10-03Restricted write access for control bits to when the core is ready.Joachim Strömbergson
2018-04-27Removed obsolete defines.Joachim Strömbergson
2018-04-27Added proper cc flags and lint flags. Cleaned up rules a bit.Joachim Strömbergson
2018-04-27Removed redundant FSM from the W memory.Joachim Strömbergson
2017-12-15Removing stale wires.Joachim Strömbergson
2017-12-15Adding lint target.Joachim Strömbergson
2017-12-08Syncecd SHA-1 core to github repo. No functional changes, but more compact ↵Joachim Strömbergson
code and a lot of minor fixes to silence warnings.
2015-12-13whack copyrightsPaul Selkirk
2015-03-31Revert streamlined wrapper, and don't delay register reads.Paul Selkirk
2015-03-17Rearrange cores.Paul Selkirk
2014-12-05There is an END to this, according to Paul.Joachim Strömbergson
2014-12-05Adding a separate digiest update state.Joachim Strömbergson
2014-11-07Adding API table.Joachim Strömbergson
2014-11-07Updated the README to hopefully make it more readable.Joachim Strömbergson
2014-11-07Changed to asynch reset.Joachim Strömbergson
2014-11-06(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing ↵Joachim Strömbergson
whitespace.
2014-04-01Update of the Python model to support NIST dual block message test as well ↵Joachim Strömbergson
as a test case with a huge message.
2014-03-17Removed redundant flag reset wires.Joachim Strömbergson
2014-03-16Added wait to allow the ready flag to be dropped with resettable flags. ↵Joachim Strömbergson
Fixed name of clock delay parameter.
2014-03-14Updating interface. Addding self resetting control regs. Fixing missing ↵Joachim Strömbergson
input port declaration that caused errors during simulation in ModelSim.
2014-02-25Adding info about the sha1 design.Joachim Strömbergson
2014-02-23Adding more info about the core.Joachim Strömbergson
2014-02-23Updated W memory module with new sliding window version. Updated README with ↵Joachim Strömbergson
more info.
2014-02-21Adding all testbenches.Joachim Strömbergson
2014-02-21Adding all rtl source files for the sha-1 core.Joachim Strömbergson
2014-02-21Adding functional model in Python. Used to drive RTL development.Joachim Strömbergson
2014-02-21Adding README file in markdown format.Joachim Strömbergson
2014-02-21Adding license file.Joachim Strömbergson
2014-02-21Adding Makefile for compiling and running simulations of the sha1 core.Joachim Strömbergson