Adding all rtl source files for the sha-1 core.

3 files changed, 1283 insertions, 0 deletions

diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
new file mode 100644
index 0000000..9d2775f
--- /dev/null
+++ b/src/rtl/sha1.v
@@ -0,0 +1,597 @@
+//======================================================================
+//
+// sha1.v
+// ------
+// Top level wrapper for the SHA-1 hash function providing
+// a simple memory like interface with 32 bit data access.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+// 
+// Redistribution and use in source and binary forms, with or 
+// without modification, are permitted provided that the following 
+// conditions are met: 
+// 
+// 1. Redistributions of source code must retain the above copyright 
+//    notice, this list of conditions and the following disclaimer. 
+// 
+// 2. Redistributions in binary form must reproduce the above copyright 
+//    notice, this list of conditions and the following disclaimer in 
+//    the documentation and/or other materials provided with the 
+//    distribution. 
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha1(
+            // Clock and reset.
+            input wire           clk,
+            input wire           reset_n,
+            
+            // Control.
+            input wire           cs,
+            input wire           write_read,
+              
+            // Data ports.
+            input wire  [7 : 0]  address,
+            input wire  [31 : 0] data_in,
+            output wire [31 : 0] data_out,
+            output wire          error
+           );
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter ADDR_NAME0       = 8'h00;
+  parameter ADDR_NAME1       = 8'h01;
+  parameter ADDR_VERSION     = 8'h02;
+
+  parameter ADDR_CTRL        = 8'h08;
+  parameter CTRL_INIT_BIT    = 0;
+  parameter CTRL_NEXT_BIT    = 1;
+
+  parameter ADDR_STATUS      = 8'h09;
+  parameter STATUS_READY_BIT = 0;
+  parameter STATUS_VALID_BIT = 1;
+                             
+  parameter ADDR_BLOCK0    = 8'h10;
+  parameter ADDR_BLOCK1    = 8'h11;
+  parameter ADDR_BLOCK2    = 8'h12;
+  parameter ADDR_BLOCK3    = 8'h13;
+  parameter ADDR_BLOCK4    = 8'h14;
+  parameter ADDR_BLOCK5    = 8'h15;
+  parameter ADDR_BLOCK6    = 8'h16;
+  parameter ADDR_BLOCK7    = 8'h17;
+  parameter ADDR_BLOCK8    = 8'h18;
+  parameter ADDR_BLOCK9    = 8'h19;
+  parameter ADDR_BLOCK10   = 8'h1a;
+  parameter ADDR_BLOCK11   = 8'h1b;
+  parameter ADDR_BLOCK12   = 8'h1c;
+  parameter ADDR_BLOCK13   = 8'h1d;
+  parameter ADDR_BLOCK14   = 8'h1e;
+  parameter ADDR_BLOCK15   = 8'h1f;
+                             
+  parameter ADDR_DIGEST0   = 8'h20;
+  parameter ADDR_DIGEST1   = 8'h21;
+  parameter ADDR_DIGEST2   = 8'h22;
+  parameter ADDR_DIGEST3   = 8'h23;
+  parameter ADDR_DIGEST4   = 8'h24;
+
+  parameter CORE_NAME0     = 32'h73686131; // "sha1"
+  parameter CORE_NAME1     = 32'h20202020; // "    "
+  parameter CORE_VERSION   = 32'h302e3530; // "0.50"
+
+  
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg init_reg;
+  reg next_reg;
+  reg ctrl_we;
+  
+  reg ready_reg;
+
+  reg [31 : 0] block0_reg;
+  reg          block0_we;
+  reg [31 : 0] block1_reg;
+  reg          block1_we;
+  reg [31 : 0] block2_reg;
+  reg          block2_we;
+  reg [31 : 0] block3_reg;
+  reg          block3_we;
+  reg [31 : 0] block4_reg;
+  reg          block4_we;
+  reg [31 : 0] block5_reg;
+  reg          block5_we;
+  reg [31 : 0] block6_reg;
+  reg          block6_we;
+  reg [31 : 0] block7_reg;
+  reg          block7_we;
+  reg [31 : 0] block8_reg;
+  reg          block8_we;
+  reg [31 : 0] block9_reg;
+  reg          block9_we;
+  reg [31 : 0] block10_reg;
+  reg          block10_we;
+  reg [31 : 0] block11_reg;
+  reg          block11_we;
+  reg [31 : 0] block12_reg;
+  reg          block12_we;
+  reg [31 : 0] block13_reg;
+  reg          block13_we;
+  reg [31 : 0] block14_reg;
+  reg          block14_we;
+  reg [31 : 0] block15_reg;
+  reg          block15_we;
+
+  reg [159 : 0] digest_reg;
+
+  reg digest_valid_reg;
+
+  
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  wire           core_init;
+  wire           core_next;
+  wire           core_ready;
+  wire [511 : 0] core_block;
+  wire [159 : 0] core_digest;
+  wire           core_digest_valid;
+
+  reg [31 : 0]   tmp_data_out;
+  reg            tmp_error;
+  
+  
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign core_init = init_reg;
+
+  assign core_next = next_reg;
+
+  assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg,
+                       block4_reg, block5_reg, block6_reg, block7_reg,
+                       block8_reg, block9_reg, block10_reg, block11_reg,
+                       block12_reg, block13_reg, block14_reg, block15_reg};
+
+  assign data_out = tmp_data_out;
+  assign error    = tmp_error;
+  
+             
+  //----------------------------------------------------------------
+  // core instantiation.
+  //----------------------------------------------------------------
+  sha1_core core(
+                   .clk(clk),
+                   .reset_n(reset_n),
+                   
+                   .init(core_init),
+                   .next(core_next),
+                  
+                   .block(core_block),
+                   
+                   .ready(core_ready),
+                   
+                   .digest(core_digest),
+                   .digest_valid(core_digest_valid)
+                  );
+  
+  
+  //----------------------------------------------------------------
+  // reg_update
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with synchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk)
+    begin
+      if (!reset_n)
+        begin
+          init_reg         <= 0;
+          next_reg         <= 0;
+          ready_reg        <= 0;
+          digest_reg       <= 160'h0000000000000000000000000000000000000000;
+          digest_valid_reg <= 0;
+          block0_reg       <= 32'h00000000;
+          block1_reg       <= 32'h00000000;
+          block2_reg       <= 32'h00000000;
+          block3_reg       <= 32'h00000000;
+          block4_reg       <= 32'h00000000;
+          block5_reg       <= 32'h00000000;
+          block6_reg       <= 32'h00000000;
+          block7_reg       <= 32'h00000000;
+          block8_reg       <= 32'h00000000;
+          block9_reg       <= 32'h00000000;
+          block10_reg      <= 32'h00000000;
+          block11_reg      <= 32'h00000000;
+          block12_reg      <= 32'h00000000;
+          block13_reg      <= 32'h00000000;
+          block14_reg      <= 32'h00000000;
+          block15_reg      <= 32'h00000000;
+        end
+      else
+        begin
+          ready_reg        <= core_ready;
+          digest_valid_reg <= core_digest_valid;
+
+          if (ctrl_we)
+            begin
+              init_reg <= data_in[CTRL_INIT_BIT];
+              next_reg <= data_in[CTRL_NEXT_BIT];
+            end
+          
+          if (core_digest_valid)
+            begin
+              digest_reg <= core_digest;
+            end
+
+          if (block0_we)
+            begin
+              block0_reg <= data_in;
+            end
+
+          if (block1_we)
+            begin
+              block1_reg <= data_in;
+            end
+
+          if (block2_we)
+            begin
+              block2_reg <= data_in;
+            end
+
+          if (block3_we)
+            begin
+              block3_reg <= data_in;
+            end
+
+          if (block4_we)
+            begin
+              block4_reg <= data_in;
+            end
+
+          if (block5_we)
+            begin
+              block5_reg <= data_in;
+            end
+
+          if (block6_we)
+            begin
+              block6_reg <= data_in;
+            end
+
+          if (block7_we)
+            begin
+              block7_reg <= data_in;
+            end
+
+          if (block8_we)
+            begin
+              block8_reg <= data_in;
+            end
+
+          if (block9_we)
+            begin
+              block9_reg <= data_in;
+            end
+
+          if (block10_we)
+            begin
+              block10_reg <= data_in;
+            end
+
+          if (block11_we)
+            begin
+              block11_reg <= data_in;
+            end
+
+          if (block12_we)
+            begin
+              block12_reg <= data_in;
+            end
+
+          if (block13_we)
+            begin
+              block13_reg <= data_in;
+            end
+
+          if (block14_we)
+            begin
+              block14_reg <= data_in;
+            end
+
+          if (block15_we)
+            begin
+              block15_reg <= data_in;
+            end
+          
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // api
+  //
+  // The interface command decoding logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : api
+      ctrl_we      = 0;
+      block0_we    = 0;
+      block1_we    = 0;
+      block2_we    = 0;
+      block3_we    = 0;
+      block4_we    = 0;
+      block5_we    = 0;
+      block6_we    = 0;
+      block7_we    = 0;
+      block8_we    = 0;
+      block9_we    = 0;
+      block10_we   = 0;
+      block11_we   = 0;
+      block12_we   = 0;
+      block13_we   = 0;
+      block14_we   = 0;
+      block15_we   = 0;
+      tmp_data_out = 32'h00000000;
+      tmp_error    = 0;
+      
+      if (cs)
+        begin
+          if (write_read)
+            begin
+              case (address)
+                // Write operations.
+                ADDR_CTRL:
+                  begin
+                    ctrl_we = 1;
+                  end
+                
+                ADDR_BLOCK0:
+                  begin
+                    block0_we = 1;
+                   end
+
+                ADDR_BLOCK1:
+                  begin
+                    block1_we = 1;
+                  end
+
+                ADDR_BLOCK2:
+                  begin
+                    block2_we = 1;
+                  end
+
+                ADDR_BLOCK3:
+                  begin
+                    block3_we = 1;
+                  end
+
+                ADDR_BLOCK4:
+                  begin
+                    block4_we = 1;
+                  end
+
+                ADDR_BLOCK5:
+                  begin
+                    block5_we = 1;
+                  end
+
+                ADDR_BLOCK6:
+                  begin
+                    block6_we = 1;
+                  end
+
+                ADDR_BLOCK7:
+                  begin
+                    block7_we = 1;
+                  end
+
+                ADDR_BLOCK8:
+                  begin
+                    block8_we = 1;
+                  end
+
+                ADDR_BLOCK9:
+                  begin
+                    block9_we = 1;
+                  end
+
+                ADDR_BLOCK10:
+                  begin
+                    block10_we = 1;
+                  end
+
+                ADDR_BLOCK11:
+                  begin
+                    block11_we = 1;
+                  end
+
+                ADDR_BLOCK12:
+                  begin
+                    block12_we = 1;
+                  end
+
+                ADDR_BLOCK13:
+                  begin
+                    block13_we = 1;
+                  end
+
+                ADDR_BLOCK14:
+                  begin
+                    block14_we = 1;
+                  end
+
+                ADDR_BLOCK15:
+                  begin
+                    block15_we = 1;
+                  end
+                
+                default:
+                  begin
+                    tmp_error = 1;
+                  end
+              endcase // case (address)
+            end // if (write_read)
+
+          else
+            begin
+              case (address)
+                // Read operations.
+                ADDR_NAME0:
+                  begin
+                    tmp_data_out = CORE_NAME0;
+                  end
+                
+                ADDR_NAME1:
+                  begin
+                    tmp_data_out = CORE_NAME1;
+                  end
+
+                ADDR_VERSION:
+                  begin
+                    tmp_data_out = CORE_VERSION;
+                  end
+
+                ADDR_CTRL:
+                  begin
+                    tmp_data_out = {28'h0000000, 2'b00, next_reg, init_reg};
+                  end
+                
+                ADDR_STATUS:
+                  begin
+                    tmp_data_out = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
+                  end
+                
+                ADDR_BLOCK0:
+                  begin
+                    tmp_data_out = block0_reg;
+                  end
+
+                ADDR_BLOCK1:
+                  begin
+                    tmp_data_out = block1_reg;
+                  end
+
+                ADDR_BLOCK2:
+                  begin
+                    tmp_data_out = block2_reg;
+                  end
+
+                ADDR_BLOCK3:
+                  begin
+                    tmp_data_out = block3_reg;
+                  end
+
+                ADDR_BLOCK4:
+                  begin
+                    tmp_data_out = block4_reg;
+                  end
+
+                ADDR_BLOCK5:
+                  begin
+                    tmp_data_out = block5_reg;
+                  end
+
+                ADDR_BLOCK6:
+                  begin
+                    tmp_data_out = block6_reg;
+                  end
+
+                ADDR_BLOCK7:
+                  begin
+                    tmp_data_out = block7_reg;
+                  end
+
+                ADDR_BLOCK8:
+                  begin
+                    tmp_data_out = block8_reg;
+                  end
+
+                ADDR_BLOCK9:
+                  begin
+                    tmp_data_out = block9_reg;
+                  end
+
+                ADDR_BLOCK10:
+                  begin
+                    tmp_data_out = block10_reg;
+                  end
+
+                ADDR_BLOCK11:
+                  begin
+                    tmp_data_out = block11_reg;
+                  end
+
+                ADDR_BLOCK12:
+                  begin
+                    tmp_data_out = block12_reg;
+                  end
+
+                ADDR_BLOCK13:
+                  begin
+                    tmp_data_out = block13_reg;
+                  end
+
+                ADDR_BLOCK14:
+                  begin
+                    tmp_data_out = block14_reg;
+                  end
+
+                ADDR_BLOCK15:
+                  begin
+                    tmp_data_out = block15_reg;
+                  end
+
+                ADDR_DIGEST0:
+                  begin
+                    tmp_data_out = digest_reg[159 : 128];
+                  end
+
+                ADDR_DIGEST1:
+                  begin
+                    tmp_data_out = digest_reg[127 :  96];
+                  end
+
+                ADDR_DIGEST2:
+                  begin
+                    tmp_data_out = digest_reg[95  :  64];
+                  end
+
+                ADDR_DIGEST3:
+                  begin
+                    tmp_data_out = digest_reg[63  :  32];
+                  end
+
+                ADDR_DIGEST4:
+                  begin
+                    tmp_data_out = digest_reg[31  :   0];
+                  end
+                
+                default:
+                  begin
+                    tmp_error = 1;
+                  end
+              endcase // case (address)
+            end
+        end
+    end // addr_decoder
+endmodule // sha1
+
+//======================================================================
+// EOF sha1.v
+//======================================================================
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v
new file mode 100644
index 0000000..be83b52
--- /dev/null
+++ b/src/rtl/sha1_core.v
@@ -0,0 +1,434 @@
+//======================================================================
+//
+// sha1_core.v
+// -----------
+// Verilog 2001 implementation of the SHA-1 hash function.
+// This is the internal core with wide interfaces.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+// 
+// Redistribution and use in source and binary forms, with or 
+// without modification, are permitted provided that the following 
+// conditions are met: 
+// 
+// 1. Redistributions of source code must retain the above copyright 
+//    notice, this list of conditions and the following disclaimer. 
+// 
+// 2. Redistributions in binary form must reproduce the above copyright 
+//    notice, this list of conditions and the following disclaimer in 
+//    the documentation and/or other materials provided with the 
+//    distribution. 
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha1_core(
+                 input wire            clk,
+                 input wire            reset_n,
+                 
+                 input wire            init,
+                 input wire            next,
+
+                 input wire [511 : 0]  block,
+                 
+                 output wire           ready,
+                  
+                 output wire [159 : 0] digest,
+                 output wire           digest_valid
+                );
+
+  
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter H0_0 = 32'h67452301;
+  parameter H0_1 = 32'hefcdab89;
+  parameter H0_2 = 32'h98badcfe;
+  parameter H0_3 = 32'h10325476;
+  parameter H0_4 = 32'hc3d2e1f0;
+
+  parameter SHA1_ROUNDS = 79;
+  
+  parameter CTRL_IDLE   = 0;
+  parameter CTRL_ROUNDS = 1;
+  parameter CTRL_DONE   = 2;
+  
+  
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [31 : 0] a_reg;
+  reg [31 : 0] a_new;
+  reg [31 : 0] b_reg;
+  reg [31 : 0] b_new;
+  reg [31 : 0] c_reg;
+  reg [31 : 0] c_new;
+  reg [31 : 0] d_reg;
+  reg [31 : 0] d_new;
+  reg [31 : 0] e_reg;
+  reg [31 : 0] e_new;
+  reg          a_e_we;
+
+  reg [31 : 0] H0_reg;
+  reg [31 : 0] H0_new;
+  reg [31 : 0] H1_reg;
+  reg [31 : 0] H1_new;
+  reg [31 : 0] H2_reg;
+  reg [31 : 0] H2_new;
+  reg [31 : 0] H3_reg;
+  reg [31 : 0] H3_new;
+  reg [31 : 0] H4_reg;
+  reg [31 : 0] H4_new;
+  reg          H_we;
+  
+  reg [6 : 0] round_ctr_reg;
+  reg [6 : 0] round_ctr_new;
+  reg         round_ctr_we;
+  reg         round_ctr_inc;
+  reg         round_ctr_rst;
+
+  reg digest_valid_reg;
+  reg digest_valid_new;
+  reg digest_valid_we;
+  
+  reg [1 : 0] sha1_ctrl_reg;
+  reg [1 : 0] sha1_ctrl_new;
+  reg         sha1_ctrl_we;
+
+  
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg           digest_init;
+  reg           digest_update;
+  reg           state_init;
+  reg           state_update;
+  reg           first_block;
+  reg           ready_flag;
+  reg           w_init;
+  wire          w_ready;
+  wire [31 : 0] w;
+              
+  
+  //----------------------------------------------------------------
+  // Module instantiantions.
+  //----------------------------------------------------------------
+  sha1_w_mem w_mem(
+                   .clk(clk),
+                   .reset_n(reset_n),
+
+                   .init(w_init),
+                   .block(block),
+                   
+                   .addr(round_ctr_reg),
+                   .w(w)
+                  );
+
+  
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign ready        = ready_flag;
+  assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
+  assign digest_valid = digest_valid_reg;
+  
+  
+  //----------------------------------------------------------------
+  // reg_update
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with synchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk)
+    begin : reg_update
+      if (!reset_n)
+        begin
+          a_reg            <= 32'h00000000;
+          b_reg            <= 32'h00000000;
+          c_reg            <= 32'h00000000;
+          d_reg            <= 32'h00000000;
+          e_reg            <= 32'h00000000;
+          H0_reg           <= 32'h00000000;
+          H1_reg           <= 32'h00000000;
+          H2_reg           <= 32'h00000000;
+          H3_reg           <= 32'h00000000;
+          H4_reg           <= 32'h00000000;
+          digest_valid_reg <= 0;
+          round_ctr_reg    <= 7'b0000000;
+          sha1_ctrl_reg    <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (a_e_we)
+            begin
+              a_reg <= a_new;
+              b_reg <= b_new;
+              c_reg <= c_new;
+              d_reg <= d_new;
+              e_reg <= e_new;
+            end
+
+          if (H_we)
+            begin
+              H0_reg <= H0_new;
+              H1_reg <= H1_new;
+              H2_reg <= H2_new;
+              H3_reg <= H3_new;
+              H4_reg <= H4_new;
+            end
+          
+          if (round_ctr_we)
+            begin
+              round_ctr_reg <= round_ctr_new;
+            end
+
+          if (digest_valid_we)
+            begin
+              digest_valid_reg <= digest_valid_new;
+            end
+          
+          if (sha1_ctrl_we)
+            begin
+              sha1_ctrl_reg <= sha1_ctrl_new;
+            end
+        end
+    end // reg_update
+
+  
+  //----------------------------------------------------------------
+  // digest_logic
+  //
+  // The logic needed to init as well as update the digest.
+  //----------------------------------------------------------------
+  always @*
+    begin : digest_logic
+      H0_new = 32'h00000000;
+      H1_new = 32'h00000000;
+      H2_new = 32'h00000000;
+      H3_new = 32'h00000000;
+      H4_new = 32'h00000000;
+      H_we = 0;
+
+      if (digest_init)
+        begin
+          H0_new = H0_0;
+          H1_new = H0_1;
+          H2_new = H0_2;
+          H3_new = H0_3;
+          H4_new = H0_4;
+          H_we = 1;
+        end
+
+      if (digest_update)
+        begin
+          H0_new = H0_reg + a_reg;
+          H1_new = H1_reg + b_reg;
+          H2_new = H2_reg + c_reg;
+          H3_new = H3_reg + d_reg;
+          H4_new = H4_reg + e_reg;
+          H_we = 1;
+        end
+    end // digest_logic
+  
+  
+  //----------------------------------------------------------------
+  // state_logic
+  //
+  // The logic needed to init as well as update the state during
+  // round processing.
+  //----------------------------------------------------------------
+  always @*
+    begin : state_logic
+      reg [31 : 0] a5;
+      reg [31 : 0] f;
+      reg [31 : 0] k;
+      reg [31 : 0] t;
+
+      a5     = 32'h00000000;
+      f      = 32'h00000000;
+      k      = 32'h00000000;
+      t      = 32'h00000000;
+      a_new  = 32'h00000000;
+      b_new  = 32'h00000000;
+      c_new  = 32'h00000000;
+      d_new  = 32'h00000000;
+      e_new  = 32'h00000000;
+      a_e_we = 0;
+      
+      if (state_init)
+        begin
+          if (first_block)
+            begin
+              a_new  = H0_0;
+              b_new  = H0_1;
+              c_new  = H0_2;
+              d_new  = H0_3;
+              e_new  = H0_4;
+              a_e_we = 1;
+            end
+          else
+            begin
+              a_new  = H0_reg;
+              b_new  = H1_reg;
+              c_new  = H2_reg;
+              d_new  = H3_reg;
+              e_new  = H4_reg;
+              a_e_we = 1;
+            end
+        end
+      
+      if (state_update)
+        begin
+          if (round_ctr_reg <= 19)
+            begin
+              k = 32'h5a827999;
+              f =  ((b_reg & c_reg) ^ (~b_reg & d_reg));
+            end
+          else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39))
+            begin
+              k = 32'h6ed9eba1;
+              f = b_reg ^ c_reg ^ d_reg;
+            end
+          else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59))
+            begin
+              k = 32'h8f1bbcdc;
+              f = ((b_reg | c_reg) ^ (b_reg | d_reg) ^ (c_reg | d_reg));
+            end
+          else if (round_ctr_reg >= 60)
+            begin
+              k = 32'hca62c1d6;
+              f = b_reg ^ c_reg ^ d_reg;
+            end
+      
+          a5 = {a_reg[26 : 0], a_reg[31 : 27]};
+          t = a5 + e_reg + f + k + w;
+
+          a_new  = t;
+          b_new  = a_reg;
+          c_new  = {b_reg[1 : 0], b_reg[31 : 2]};
+          d_new  = c_reg;
+          e_new  = d_reg;
+          a_e_we = 1;
+        end
+    end // state_logic
+
+  
+  //----------------------------------------------------------------
+  // round_ctr
+  //
+  // Update logic for the round counter, a monotonically 
+  // increasing counter with reset.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_ctr
+      round_ctr_new = 0;
+      round_ctr_we  = 0;
+      
+      if (round_ctr_rst)
+        begin
+          round_ctr_new = 0;
+          round_ctr_we  = 1;
+        end
+
+      if (round_ctr_inc)
+        begin
+          round_ctr_new = round_ctr_reg + 1'b1;
+          round_ctr_we  = 1;
+        end
+    end // round_ctr
+
+  
+  //----------------------------------------------------------------
+  // sha1_ctrl_fsm
+  // Logic for the state machine controlling the core behaviour.
+  //----------------------------------------------------------------
+  always @*
+    begin : sha1_ctrl_fsm
+      digest_init      = 0;
+      digest_update    = 0;
+      state_init       = 0;
+      state_update     = 0;
+      first_block      = 0;
+      ready_flag       = 0;
+      w_init           = 0;
+      round_ctr_inc    = 0;
+      round_ctr_rst    = 0;
+      digest_valid_new = 0;
+      digest_valid_we  = 0;
+      sha1_ctrl_new    = CTRL_IDLE;
+      sha1_ctrl_we     = 0;
+      
+      case (sha1_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            ready_flag = 1;
+            
+            if (init)
+              begin
+                digest_init      = 1;
+                w_init           = 1;
+                state_init       = 1;
+                first_block      = 1;
+                round_ctr_rst    = 1;
+                digest_valid_new = 0;
+                digest_valid_we  = 1;
+                sha1_ctrl_new    = CTRL_ROUNDS;
+                sha1_ctrl_we     = 1;
+              end
+
+            if (next)
+              begin
+                w_init           = 1;
+                state_init       = 1;
+                round_ctr_rst    = 1;
+                digest_valid_new = 0;
+                digest_valid_we  = 1;
+                sha1_ctrl_new    = CTRL_ROUNDS;
+                sha1_ctrl_we     = 1;
+              end
+          end
+
+        
+        CTRL_ROUNDS:
+          begin
+            state_update  = 1;
+            round_ctr_inc = 1;
+
+            if (round_ctr_reg == SHA1_ROUNDS)
+              begin
+                sha1_ctrl_new = CTRL_DONE;
+                sha1_ctrl_we  = 1;
+              end
+          end
+
+        
+        CTRL_DONE:
+          begin
+            digest_update    = 1;
+            digest_valid_new = 1;
+            digest_valid_we  = 1;
+            sha1_ctrl_new    = CTRL_IDLE;
+            sha1_ctrl_we     = 1;
+          end
+      endcase // case (sha1_ctrl_reg)
+    end // sha1_ctrl_fsm
+    
+endmodule // sha1_core
+
+//======================================================================
+// EOF sha1_core.v
+//======================================================================
diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v
new file mode 100644
index 0000000..9aaa403
--- /dev/null
+++ b/src/rtl/sha1_w_mem.v
@@ -0,0 +1,252 @@
+//======================================================================
+//
+// sha1_w_mem_reg.v
+// -----------------
+// The SHA-1 W memory. This memory includes functionality to 
+// expand the block into 80 words.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+// 
+// Redistribution and use in source and binary forms, with or 
+// without modification, are permitted provided that the following 
+// conditions are met: 
+// 
+// 1. Redistributions of source code must retain the above copyright 
+//    notice, this list of conditions and the following disclaimer. 
+// 
+// 2. Redistributions in binary form must reproduce the above copyright 
+//    notice, this list of conditions and the following disclaimer in 
+//    the documentation and/or other materials provided with the 
+//    distribution. 
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha1_w_mem(
+                  input wire           clk,
+                  input wire           reset_n,
+
+                  input wire           init,
+                  input wire [511 : 0] block,
+
+                  input wire [6 : 0]   addr,
+                  output wire [31 : 0] w
+                 );
+
+  
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter SHA1_ROUNDS = 79;
+
+  parameter CTRL_IDLE   = 1'b0;
+  parameter CTRL_UPDATE = 1'b1;
+
+  
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [31 : 0] w_mem [0 : 79];
+  reg [31 : 0] w_mem_new;
+  reg          w_mem_we;
+  
+  reg [6 : 0] w_ctr_reg;
+  reg [6 : 0] w_ctr_new;
+  reg         w_ctr_we;
+  reg         w_ctr_inc;
+  reg         w_ctr_set;
+  
+  reg         sha1_w_mem_ctrl_reg;
+  reg         sha1_w_mem_ctrl_new;
+  reg         sha1_w_mem_ctrl_we;
+  
+  
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [31 : 0] w_tmp;
+  reg [31 : 0] w_new;
+  reg [6 : 0]  w_addr;
+  reg          w_update;
+  
+  
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign w     = w_tmp;
+  
+  
+  //----------------------------------------------------------------
+  // reg_update
+  //
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with synchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk)
+    begin : reg_update
+      if (!reset_n)
+        begin
+          w_ctr_reg           <= 7'b0000000;
+          sha1_w_mem_ctrl_reg <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (init)
+            begin
+              w_mem[00] <= block[511 : 480];
+              w_mem[01] <= block[479 : 448];
+              w_mem[02] <= block[447 : 416];
+              w_mem[03] <= block[415 : 384];
+              w_mem[04] <= block[383 : 352];
+              w_mem[05] <= block[351 : 320];
+              w_mem[06] <= block[319 : 288];
+              w_mem[07] <= block[287 : 256];
+              w_mem[08] <= block[255 : 224];
+              w_mem[09] <= block[223 : 192];
+              w_mem[10] <= block[191 : 160];
+              w_mem[11] <= block[159 : 128];
+              w_mem[12] <= block[127 :  96];
+              w_mem[13] <= block[95  :  64];
+              w_mem[14] <= block[63  :  32];
+              w_mem[15] <= block[31  :   0];
+            end
+
+          if (w_mem_we)
+            begin
+              w_mem[w_addr] <= w_mem_new;
+            end
+          
+          if (w_ctr_we)
+            begin
+              w_ctr_reg <= w_ctr_new;
+            end
+          
+          if (sha1_w_mem_ctrl_we)
+            begin
+              sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
+            end
+
+        end
+    end // reg_update
+
+  
+  //----------------------------------------------------------------
+  // external_addr_mux
+  //
+  // Mux for the external read operation. This is where we exract
+  // the W variable.
+  //----------------------------------------------------------------
+  always @*
+    begin : external_addr_mux
+      w_tmp = w_mem[addr];
+    end // external_addr_mux
+  
+
+  //----------------------------------------------------------------
+  // w_schedule
+  //
+  // W word expansion logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : w_schedule
+      reg [31 : 0] w_new_tmp;
+      
+      w_mem_we  = 0;
+      w_new_tmp = 32'h00000000;
+      w_mem_new = 32'h00000000;
+      w_addr    = 0;
+
+      if (w_update)
+        begin
+          w_new_tmp = w_mem[(w_ctr_reg - 3)] ^ w_mem[(w_ctr_reg - 8)] ^
+                      w_mem[(w_ctr_reg - 14)] ^ w_mem[(w_ctr_reg - 16)];
+          w_mem_new = {w_new_tmp[30 : 0], w_new_tmp[31]};
+          w_addr    = w_ctr_reg;
+          w_mem_we  = 1;
+        end
+    end // w_schedule
+
+  
+  //----------------------------------------------------------------
+  // w_ctr
+  //
+  // W schedule adress counter. Counts from 0x10 to 0x3f and
+  // is used to expand the block into words.
+  //----------------------------------------------------------------
+  always @*
+    begin : w_ctr
+      w_ctr_new = 0;
+      w_ctr_we  = 0;
+      
+      if (w_ctr_set)
+        begin
+          w_ctr_new = 6'h10;
+          w_ctr_we  = 1;
+        end
+
+      if (w_ctr_inc)
+        begin
+          w_ctr_new = w_ctr_reg + 6'h01;
+          w_ctr_we  = 1;
+        end
+    end // w_ctr
+
+  
+  //----------------------------------------------------------------
+  // sha1_w_mem_fsm
+  //
+  // Logic for the w shedule FSM.
+  //----------------------------------------------------------------
+  always @*
+    begin : sha1_w_mem_fsm
+      w_ctr_set = 0;
+      w_ctr_inc = 0;
+      w_update  = 0;
+      
+      sha1_w_mem_ctrl_new = CTRL_IDLE;
+      sha1_w_mem_ctrl_we  = 0;
+      
+      case (sha1_w_mem_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            if (init)
+              begin
+                w_ctr_set           = 1;
+                sha1_w_mem_ctrl_new = CTRL_UPDATE;
+                sha1_w_mem_ctrl_we  = 1;
+              end
+          end
+        
+        CTRL_UPDATE:
+          begin
+            w_update  = 1;
+            w_ctr_inc = 1;
+
+            if (w_ctr_reg == SHA1_ROUNDS)
+              begin
+                sha1_w_mem_ctrl_new = CTRL_IDLE;
+                sha1_w_mem_ctrl_we  = 1;
+              end
+          end
+      endcase // case (sha1_ctrl_reg)
+    end // sha1_ctrl_fsm
+endmodule // sha1_w_mem
+
+//======================================================================
+// sha1_w_mem.v
+//======================================================================