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+sha1
+====
+
+## Introduction ##
+Verilog implementation of the SHA-1 cryptgraphic hash function.
+The implementaion follows the specification in NIST FIPS 180-4.
+
+This core is based on the project at:
+https://github.com/secworks/sha1
+
+
+## Implementation details ##
+
+### Altera Cyclone IV GX ###
+Implementation using Altera Quartus-II 13.1 with a EP4CGX22CF19C6 device
+as target.
+* 10718 LEs
+* 3575 Regs
+* 103 MHz
+
+
+## TODO ##
+* Extensive functional verification in real HW.
+* Add Wishbone interface.
+* Documentation
+
+
+## Status ##
+***(2014-02-21):***
+
+Moved the core to Cryptech.