core/hash/sha1 - Verilog implementation of the SHA-1 cryptographic hash function

Age	Commit message (Collapse)	Author
2014-03-16	Added wait to allow the ready flag to be dropped with resettable flags. ↵	Joachim Strömbergson
	Fixed name of clock delay parameter.
2014-03-14	Updating interface. Addding self resetting control regs. Fixing missing ↵	Joachim Strömbergson
	input port declaration that caused errors during simulation in ModelSim.
2014-02-25	Adding info about the sha1 design.	Joachim Strömbergson

2014-02-23	Adding more info about the core.	Joachim Strömbergson

2014-02-23	Updated W memory module with new sliding window version. Updated README with ↵	Joachim Strömbergson
	more info.
2014-02-21	Adding all testbenches.	Joachim Strömbergson

2014-02-21	Adding all rtl source files for the sha-1 core.	Joachim Strömbergson

2014-02-21	Adding functional model in Python. Used to drive RTL development.	Joachim Strömbergson

2014-02-21	Adding README file in markdown format.	Joachim Strömbergson

2014-02-21	Adding license file.	Joachim Strömbergson

2014-02-21	Adding Makefile for compiling and running simulations of the sha1 core.	Joachim Strömbergson