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-rw-r--r--src/tb/tb_sha1.v496
-rw-r--r--src/tb/tb_sha1_core.v386
-rw-r--r--src/tb/tb_sha1_w_mem.v328
3 files changed, 1210 insertions, 0 deletions
diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v
new file mode 100644
index 0000000..632b4e9
--- /dev/null
+++ b/src/tb/tb_sha1.v
@@ -0,0 +1,496 @@
+//======================================================================
+//
+// tb_sha1.v
+// ---------
+// Testbench for the SHA-1 top level wrapper.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/10ps
+
+module tb_sha1();
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter DEBUG = 0;
+
+ parameter CLK_HALF_PERIOD = 2;
+
+ parameter ADDR_NAME0 = 8'h00;
+ parameter ADDR_NAME1 = 8'h01;
+ parameter ADDR_VERSION = 8'h02;
+
+ parameter ADDR_CTRL = 8'h08;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+ parameter CTRL_INIT_VALUE = 8'h01;
+ parameter CTRL_NEXT_VALUE = 8'h02;
+
+ parameter ADDR_STATUS = 8'h09;
+ parameter STATUS_READY_BIT = 0;
+ parameter STATUS_VALID_BIT = 1;
+
+ parameter ADDR_BLOCK0 = 8'h10;
+ parameter ADDR_BLOCK1 = 8'h11;
+ parameter ADDR_BLOCK2 = 8'h12;
+ parameter ADDR_BLOCK3 = 8'h13;
+ parameter ADDR_BLOCK4 = 8'h14;
+ parameter ADDR_BLOCK5 = 8'h15;
+ parameter ADDR_BLOCK6 = 8'h16;
+ parameter ADDR_BLOCK7 = 8'h17;
+ parameter ADDR_BLOCK8 = 8'h18;
+ parameter ADDR_BLOCK9 = 8'h19;
+ parameter ADDR_BLOCK10 = 8'h1a;
+ parameter ADDR_BLOCK11 = 8'h1b;
+ parameter ADDR_BLOCK12 = 8'h1c;
+ parameter ADDR_BLOCK13 = 8'h1d;
+ parameter ADDR_BLOCK14 = 8'h1e;
+ parameter ADDR_BLOCK15 = 8'h1f;
+
+ parameter ADDR_DIGEST0 = 8'h20;
+ parameter ADDR_DIGEST1 = 8'h21;
+ parameter ADDR_DIGEST2 = 8'h22;
+ parameter ADDR_DIGEST3 = 8'h23;
+ parameter ADDR_DIGEST4 = 8'h24;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_cs;
+ reg tb_write_read;
+ reg [7 : 0] tb_address;
+ reg [31 : 0] tb_data_in;
+ wire [31 : 0] tb_data_out;
+
+ reg [31 : 0] read_data;
+ reg [159 : 0] digest_data;
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ sha1 dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .cs(tb_cs),
+ .write_read(tb_write_read),
+
+ .address(tb_address),
+ .data_in(tb_data_in),
+ .data_out(tb_data_out)
+ );
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //----------------------------------------------------------------
+ // sys_monitor
+ //----------------------------------------------------------------
+ always
+ begin : sys_monitor
+ #(2 * CLK_HALF_PERIOD);
+ cycle_ctr = cycle_ctr + 1;
+ end
+
+
+ //----------------------------------------------------------------
+ // dump_dut_state()
+ //
+ // Dump the state of the dump when needed.
+ //----------------------------------------------------------------
+ task dump_dut_state();
+ begin
+ end
+ endtask // dump_dut_state
+
+
+ //----------------------------------------------------------------
+ // reset_dut()
+ //----------------------------------------------------------------
+ task reset_dut();
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(4 * CLK_HALF_PERIOD);
+ tb_reset_n = 1;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // init_sim()
+ //
+ // Initialize all counters and testbed functionality as well
+ // as setting the DUT inputs to defined values.
+ //----------------------------------------------------------------
+ task init_sim();
+ begin
+ cycle_ctr = 32'h00000000;
+ error_ctr = 32'h00000000;
+ tc_ctr = 32'h00000000;
+
+ tb_clk = 0;
+ tb_reset_n = 0;
+ tb_cs = 0;
+ tb_write_read = 0;
+ tb_address = 6'h00;
+ tb_data_in = 32'h00000000;
+ end
+ endtask // init_dut
+
+
+ //----------------------------------------------------------------
+ // display_test_result()
+ //
+ // Display the accumulated test results.
+ //----------------------------------------------------------------
+ task display_test_result();
+ begin
+ if (error_ctr == 0)
+ begin
+ $display("*** All %02d test cases completed successfully.", tc_ctr);
+ end
+ else
+ begin
+ $display("*** %02d test cases completed.", tc_ctr);
+ $display("*** %02d errors detected during testing.", error_ctr);
+ end
+ end
+ endtask // display_test_result
+
+
+ //----------------------------------------------------------------
+ // wait_ready()
+ //
+ // Wait for the ready flag in the dut to be set.
+ // (Actually we wait for either ready or valid to be set.)
+ //
+ // Note: It is the callers responsibility to call the function
+ // when the dut is actively processing and will in fact at some
+ // point set the flag.
+ //----------------------------------------------------------------
+ task wait_ready();
+ begin
+ read_data = 0;
+
+ while (read_data == 0)
+ begin
+ read_word(ADDR_STATUS);
+ end
+ end
+ endtask // wait_ready
+
+
+ //----------------------------------------------------------------
+ // read_word()
+ //
+ // Read a data word from the given address in the DUT.
+ // the word read will be available in the global variable
+ // read_data.
+ //----------------------------------------------------------------
+ task read_word(input [7 : 0] address);
+ begin
+ tb_address = address;
+ tb_cs = 1;
+ tb_write_read = 0;
+ #(2 * CLK_HALF_PERIOD);
+ read_data = tb_data_out;
+ tb_cs = 0;
+
+ if (DEBUG)
+ begin
+ $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
+ $display("");
+ end
+ end
+ endtask // read_word
+
+
+ //----------------------------------------------------------------
+ // write_word()
+ //
+ // Write the given word to the DUT using the DUT interface.
+ //----------------------------------------------------------------
+ task write_word(input [7 : 0] address,
+ input [31 : 0] word);
+ begin
+ if (DEBUG)
+ begin
+ $display("*** Writing 0x%08x to 0x%02x.", word, address);
+ $display("");
+ end
+
+ tb_address = address;
+ tb_data_in = word;
+ tb_cs = 1;
+ tb_write_read = 1;
+ #(2 * CLK_HALF_PERIOD);
+ tb_cs = 0;
+ tb_write_read = 0;
+ end
+ endtask // write_word
+
+
+ //----------------------------------------------------------------
+ // write_block()
+ //
+ // Write the given block to the dut.
+ //----------------------------------------------------------------
+ task write_block(input [511 : 0] block);
+ begin
+ write_word(ADDR_BLOCK0, block[511 : 480]);
+ write_word(ADDR_BLOCK1, block[479 : 448]);
+ write_word(ADDR_BLOCK2, block[447 : 416]);
+ write_word(ADDR_BLOCK3, block[415 : 384]);
+ write_word(ADDR_BLOCK4, block[383 : 352]);
+ write_word(ADDR_BLOCK5, block[351 : 320]);
+ write_word(ADDR_BLOCK6, block[319 : 288]);
+ write_word(ADDR_BLOCK7, block[287 : 256]);
+ write_word(ADDR_BLOCK8, block[255 : 224]);
+ write_word(ADDR_BLOCK9, block[223 : 192]);
+ write_word(ADDR_BLOCK10, block[191 : 160]);
+ write_word(ADDR_BLOCK11, block[159 : 128]);
+ write_word(ADDR_BLOCK12, block[127 : 96]);
+ write_word(ADDR_BLOCK13, block[95 : 64]);
+ write_word(ADDR_BLOCK14, block[63 : 32]);
+ write_word(ADDR_BLOCK15, block[31 : 0]);
+ end
+ endtask // write_block
+
+
+ //----------------------------------------------------------------
+ // check_name_version()
+ //
+ // Read the name and version from the DUT.
+ //----------------------------------------------------------------
+ task check_name_version();
+ reg [31 : 0] name0;
+ reg [31 : 0] name1;
+ reg [31 : 0] version;
+ begin
+
+ read_word(ADDR_NAME0);
+ name0 = read_data;
+ read_word(ADDR_NAME1);
+ name1 = read_data;
+ read_word(ADDR_VERSION);
+ version = read_data;
+
+ $display("DUT name: %c%c%c%c%c%c%c%c",
+ name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
+ name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
+ $display("DUT version: %c%c%c%c",
+ version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
+ end
+ endtask // check_name_version
+
+
+ //----------------------------------------------------------------
+ // read_digest()
+ //
+ // Read the digest in the dut. The resulting digest will be
+ // available in the global variable digest_data.
+ //----------------------------------------------------------------
+ task read_digest();
+ begin
+ read_word(ADDR_DIGEST0);
+ digest_data[159 : 128] = read_data;
+ read_word(ADDR_DIGEST1);
+ digest_data[127 : 96] = read_data;
+ read_word(ADDR_DIGEST2);
+ digest_data[95 : 64] = read_data;
+ read_word(ADDR_DIGEST3);
+ digest_data[63 : 32] = read_data;
+ read_word(ADDR_DIGEST4);
+ digest_data[31 : 0] = read_data;
+ end
+ endtask // read_digest
+
+
+ //----------------------------------------------------------------
+ // single_block_test()
+ //
+ //
+ // Perform test of a single block digest.
+ //----------------------------------------------------------------
+ task single_block_test([511 : 0] block,
+ [159 : 0] expected);
+ begin
+ $display("*** TC%01d - Single block test started.", tc_ctr);
+
+ write_block(block);
+ write_word(ADDR_CTRL, CTRL_INIT_VALUE);
+ write_word(ADDR_CTRL, 8'h00);
+ wait_ready();
+ read_digest();
+
+ if (digest_data == expected)
+ begin
+ $display("TC%01d: OK.", tc_ctr);
+ end
+ else
+ begin
+ $display("TC%01d: ERROR.", tc_ctr);
+ $display("TC%01d: Expected: 0x%040x", tc_ctr, expected);
+ $display("TC%01d: Got: 0x%040x", tc_ctr, digest_data);
+ error_ctr = error_ctr + 1;
+ end
+ $display("*** TC%01d - Single block test done.", tc_ctr);
+ tc_ctr = tc_ctr + 1;
+ end
+ endtask // single_block_test
+
+
+ //----------------------------------------------------------------
+ // double_block_test()
+ //
+ //
+ // Perform test of a double block digest. Note that we check
+ // the digests for both the first and final block.
+ //----------------------------------------------------------------
+ task double_block_test([511 : 0] block0,
+ [159 : 0] expected0,
+ [511 : 0] block1,
+ [159 : 0] expected1
+ );
+ begin
+ $display("*** TC%01d - Double block test started.", tc_ctr);
+
+ // First block
+ write_block(block0);
+ write_word(ADDR_CTRL, CTRL_INIT_VALUE);
+ write_word(ADDR_CTRL, 8'h00);
+ wait_ready();
+ read_digest();
+
+ if (digest_data == expected0)
+ begin
+ $display("TC%01d first block: OK.", tc_ctr);
+ end
+ else
+ begin
+ $display("TC%01d: ERROR in first digest", tc_ctr);
+ $display("TC%01d: Expected: 0x%040x", tc_ctr, expected0);
+ $display("TC%01d: Got: 0x%040x", tc_ctr, digest_data);
+ error_ctr = error_ctr + 1;
+ end
+
+ // Final block
+ write_block(block1);
+ write_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+ write_word(ADDR_CTRL, 8'h00);
+ wait_ready();
+ read_digest();
+
+ if (digest_data == expected1)
+ begin
+ $display("TC%01d final block: OK.", tc_ctr);
+ end
+ else
+ begin
+ $display("TC%01d: ERROR in final digest", tc_ctr);
+ $display("TC%01d: Expected: 0x%040x", tc_ctr, expected1);
+ $display("TC%01d: Got: 0x%040x", tc_ctr, digest_data);
+ error_ctr = error_ctr + 1;
+ end
+
+ $display("*** TC%01d - Double block test done.", tc_ctr);
+ tc_ctr = tc_ctr + 1;
+ end
+ endtask // double_block_test
+
+
+ //----------------------------------------------------------------
+ // sha1_test
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : sha1_test
+ reg [511 : 0] tc1;
+ reg [159 : 0] res1;
+
+ reg [511 : 0] tc2_1;
+ reg [159 : 0] res2_1;
+ reg [511 : 0] tc2_2;
+ reg [159 : 0] res2_2;
+
+ $display(" -- Testbench for sha1 started --");
+
+ init_sim();
+ reset_dut();
+ check_name_version();
+
+ // TC1: Single block message: "abc".
+ tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
+ res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d;
+ single_block_test(tc1, res1);
+
+ // TC2: Double block message.
+ // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
+ tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
+ res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572;
+
+ tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
+ res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1;
+ double_block_test(tc2_1, res2_1, tc2_2, res2_2);
+
+ display_test_result();
+ $display("*** Simulation done. ***");
+ $finish;
+ end // sha1_test
+endmodule // tb_sha1
+
+//======================================================================
+// EOF tb_sha1.v
+//======================================================================
+
diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v
new file mode 100644
index 0000000..8a5d11b
--- /dev/null
+++ b/src/tb/tb_sha1_core.v
@@ -0,0 +1,386 @@
+//======================================================================
+//
+// tb_sha1_core.v
+// ----------------
+// Testbench for the SHA-1 core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/10ps
+
+module tb_sha1_core();
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter DEBUG = 0;
+
+ parameter CLK_HALF_PERIOD = 2;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_init;
+ reg tb_next;
+ reg [511 : 0] tb_block;
+ wire tb_ready;
+ wire [159 : 0] tb_digest;
+ wire tb_digest_valid;
+
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ sha1_core dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .init(tb_init),
+ .next(tb_next),
+
+ .block(tb_block),
+
+ .ready(tb_ready),
+
+ .digest(tb_digest),
+ .digest_valid(tb_digest_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //----------------------------------------------------------------
+ // sys_monitor
+ //----------------------------------------------------------------
+ always
+ begin : sys_monitor
+ #(2 * CLK_HALF_PERIOD);
+ if (DEBUG)
+ begin
+ dump_dut_state();
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // dump_dut_state()
+ //
+ // Dump the state of the dump when needed.
+ //----------------------------------------------------------------
+ task dump_dut_state();
+ begin
+ $display("State of DUT");
+ $display("------------");
+ $display("Inputs and outputs:");
+ $display("init = 0x%01x, next = 0x%01x",
+ dut.init, dut.next);
+ $display("block = 0x%0128x", dut.block);
+
+ $display("ready = 0x%01x, valid = 0x%01x",
+ dut.ready, dut.digest_valid);
+ $display("digest = 0x%040x", dut.digest);
+ $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
+ dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);
+ $display("");
+
+ $display("Control signals and counter:");
+ $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg);
+ $display("digest_init = 0x%01x, digest_update = 0x%01x",
+ dut.digest_init, dut.digest_update);
+ $display("state_init = 0x%01x, state_update = 0x%01x",
+ dut.state_init, dut.state_update);
+ $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
+ dut.first_block, dut.ready_flag, dut.w_init);
+ $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
+ dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);
+ $display("");
+
+ $display("State registers:");
+ $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
+ dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg, dut.e_reg);
+ $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
+ dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);
+ $display("");
+
+ $display("State update values:");
+ $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
+ dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);
+ $display("");
+ end
+ endtask // dump_dut_state
+
+
+ //----------------------------------------------------------------
+ // reset_dut()
+ //----------------------------------------------------------------
+ task reset_dut();
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(4 * CLK_HALF_PERIOD);
+ tb_reset_n = 1;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // init_sim()
+ //
+ // Initialize all counters and testbed functionality as well
+ // as setting the DUT inputs to defined values.
+ //----------------------------------------------------------------
+ task init_sim();
+ begin
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
+
+ tb_init = 0;
+ tb_next = 0;
+ tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ end
+ endtask // init_dut
+
+
+ //----------------------------------------------------------------
+ // display_test_result()
+ //
+ // Display the accumulated test results.
+ //----------------------------------------------------------------
+ task display_test_result();
+ begin
+ if (error_ctr == 0)
+ begin
+ $display("*** All %02d test cases completed successfully", tc_ctr);
+ end
+ else
+ begin
+ $display("*** %02d test cases did not complete successfully.", error_ctr);
+ end
+ end
+ endtask // display_test_result
+
+
+ //----------------------------------------------------------------
+ // wait_ready()
+ //
+ // Wait for the ready flag in the dut to be set.
+ //
+ // Note: It is the callers responsibility to call the function
+ // when the dut is actively processing and will in fact at some
+ // point set the flag.
+ //----------------------------------------------------------------
+ task wait_ready();
+ begin
+ while (!tb_ready)
+ begin
+ #(2 * CLK_HALF_PERIOD);
+
+ end
+ end
+ endtask // wait_ready
+
+
+ //----------------------------------------------------------------
+ // single_block_test
+ //
+ // Test a message of at most one block.
+ //----------------------------------------------------------------
+ task single_block_test(input [7 : 0] tc_number,
+ input [511 : 0] block,
+ input [159 : 0] expected);
+ begin
+ $display("*** TC %0d single block test case started.", tc_number);
+ tc_ctr = tc_ctr + 1;
+
+ tb_block = block;
+ tb_init = 1;
+ #(2 * CLK_HALF_PERIOD);
+ tb_init = 0;
+ wait_ready();
+
+
+ if (tb_digest == expected)
+ begin
+ $display("*** TC %0d successful.", tc_number);
+ $display("");
+ end
+ else
+ begin
+ $display("*** ERROR: TC %0d NOT successful.", tc_number);
+ $display("Expected: 0x%040x", expected);
+ $display("Got: 0x%040x", tb_digest);
+ $display("");
+
+ error_ctr = error_ctr + 1;
+ end
+ end
+ endtask // single_block_test
+
+
+ //----------------------------------------------------------------
+ // double_block_test
+ //
+ // Test message consisting of two blocks.
+ //----------------------------------------------------------------
+ task double_block_test(input [7 : 0] tc_number,
+ input [511 : 0] block1,
+ input [159 : 0] expected1,
+ input [511 : 0] block2,
+ input [159 : 0] expected2);
+
+ reg [159 : 0] db_digest1;
+ reg db_error;
+ begin
+ $display("*** TC %0d double block test case started.", tc_number);
+ db_error = 0;
+ tc_ctr = tc_ctr + 1;
+
+ $display("*** TC %0d first block started.", tc_number);
+ tb_block = block1;
+ tb_init = 1;
+ #(2 * CLK_HALF_PERIOD);
+ tb_init = 0;
+ wait_ready();
+ db_digest1 = tb_digest;
+ $display("*** TC %0d first block done.", tc_number);
+
+ $display("*** TC %0d second block started.", tc_number);
+ tb_block = block2;
+ tb_next = 1;
+ #(2 * CLK_HALF_PERIOD);
+ tb_next = 0;
+ wait_ready();
+ $display("*** TC %0d second block done.", tc_number);
+
+ if (db_digest1 == expected1)
+ begin
+ $display("*** TC %0d first block successful", tc_number);
+ $display("");
+ end
+ else
+ begin
+ $display("*** ERROR: TC %0d first block NOT successful", tc_number);
+ $display("Expected: 0x%040x", expected1);
+ $display("Got: 0x%040x", db_digest1);
+ $display("");
+ db_error = 1;
+ end
+
+ if (db_digest1 == expected1)
+ begin
+ $display("*** TC %0d second block successful", tc_number);
+ $display("");
+ end
+ else
+ begin
+ $display("*** ERROR: TC %0d second block NOT successful", tc_number);
+ $display("Expected: 0x%040x", expected2);
+ $display("Got: 0x%040x", tb_digest);
+ $display("");
+ db_error = 1;
+ end
+
+ if (db_error)
+ begin
+ error_ctr = error_ctr + 1;
+ end
+ end
+ endtask // double_block_test
+
+
+ //----------------------------------------------------------------
+ // sha1_core_test
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : sha1_core_test
+ reg [511 : 0] tc1;
+ reg [159 : 0] res1;
+
+ reg [511 : 0] tc2_1;
+ reg [159 : 0] res2_1;
+ reg [511 : 0] tc2_2;
+ reg [159 : 0] res2_2;
+
+ $display(" -- Testbench for sha1 core started --");
+
+ init_sim();
+ dump_dut_state();
+ reset_dut();
+ dump_dut_state();
+
+ // TC1: Single block message: "abc".
+ tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
+ res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d;
+ single_block_test(1, tc1, res1);
+
+ // TC2: Double block message.
+ // "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
+ tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
+ res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572;
+
+ tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
+ res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1;
+ double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);
+
+ display_test_result();
+ $display("*** Simulation done.");
+ $finish;
+ end // sha1_core_test
+endmodule // tb_sha1_core
+
+//======================================================================
+// EOF tb_sha1_core.v
+//======================================================================
diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v
new file mode 100644
index 0000000..233e409
--- /dev/null
+++ b/src/tb/tb_sha1_w_mem.v
@@ -0,0 +1,328 @@
+//======================================================================
+//
+// Tb_sha1_w_mem.v
+// ---------------
+// Testbench for the SHA-1 W memory module.
+// This testbench is currently not self testing.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/10ps
+
+module tb_sha1_w_mem();
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter DEBUG = 1;
+ parameter DISPLAY_CYCLES = 0;
+
+ parameter CLK_HALF_PERIOD = 2;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_init;
+ reg [511 : 0] tb_block;
+ reg [6 : 0] tb_addr;
+ wire [31 : 0] tb_w;
+
+ reg [63 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ sha1_w_mem dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .init(tb_init),
+ .block(tb_block),
+
+ .addr(tb_addr),
+ .w(tb_w)
+ );
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //--------------------------------------------------------------------
+ // dut_monitor
+ //
+ // Monitor displaying information every cycle.
+ // Includes the cycle counter.
+ //--------------------------------------------------------------------
+ always @ (posedge tb_clk)
+ begin : dut_monitor
+ cycle_ctr = cycle_ctr + 1;
+
+ if (DISPLAY_CYCLES)
+ begin
+ $display("cycle = %016x:", cycle_ctr);
+ end
+
+ if (DEBUG)
+ begin
+ $display("addr: 0x%02x:", dut.addr);
+ $display("addr4: 0x%02x:", dut.addr[3 : 0]);
+ $display("w_mem_new: 0x%08x:", dut.w_mem_new);
+ $display("w_mem_we: 0x%x:", dut.w_mem_we);
+ end
+ end // dut_monitor
+
+
+ //----------------------------------------------------------------
+ // dump_w_state()
+ //
+ // Dump the current state of all W registers.
+ //----------------------------------------------------------------
+ task dump_w_state();
+ begin
+ $display("W state:");
+
+ $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x",
+ dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);
+
+ $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x",
+ dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);
+
+ $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x",
+ dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);
+
+ $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
+ dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);
+
+ $display("w16_reg = %08x, w17_reg = %08x, w18_reg = %08x, w19_reg = %08x",
+ dut.w_mem[16], dut.w_mem[17], dut.w_mem[18], dut.w_mem[19]);
+
+ $display("w20_reg = %08x, w21_reg = %08x, w22_reg = %08x, w23_reg = %08x",
+ dut.w_mem[20], dut.w_mem[21], dut.w_mem[22], dut.w_mem[23]);
+
+ $display("w24_reg = %08x, w25_reg = %08x, w26_reg = %08x, w27_reg = %08x",
+ dut.w_mem[24], dut.w_mem[25], dut.w_mem[26], dut.w_mem[27]);
+
+ $display("w28_reg = %08x, w29_reg = %08x, w30_reg = %08x, w31_reg = %08x",
+ dut.w_mem[28], dut.w_mem[29], dut.w_mem[30], dut.w_mem[31]);
+
+ $display("w32_reg = %08x, w33_reg = %08x, w34_reg = %08x, w35_reg = %08x",
+ dut.w_mem[32], dut.w_mem[33], dut.w_mem[34], dut.w_mem[35]);
+
+ $display("w36_reg = %08x, w37_reg = %08x, w38_reg = %08x, w39_reg = %08x",
+ dut.w_mem[36], dut.w_mem[37], dut.w_mem[38], dut.w_mem[39]);
+
+ $display("w40_reg = %08x, w41_reg = %08x, w42_reg = %08x, w43_reg = %08x",
+ dut.w_mem[40], dut.w_mem[41], dut.w_mem[42], dut.w_mem[43]);
+
+ $display("w44_reg = %08x, w45_reg = %08x, w46_reg = %08x, w47_reg = %08x",
+ dut.w_mem[44], dut.w_mem[45], dut.w_mem[46], dut.w_mem[47]);
+
+ $display("w48_reg = %08x, w49_reg = %08x, w50_reg = %08x, w51_reg = %08x",
+ dut.w_mem[48], dut.w_mem[49], dut.w_mem[50], dut.w_mem[51]);
+
+ $display("w52_reg = %08x, w53_reg = %08x, w54_reg = %08x, w55_reg = %08x",
+ dut.w_mem[52], dut.w_mem[53], dut.w_mem[54], dut.w_mem[55]);
+
+ $display("w56_reg = %08x, w57_reg = %08x, w58_reg = %08x, w59_reg = %08x",
+ dut.w_mem[56], dut.w_mem[57], dut.w_mem[58], dut.w_mem[59]);
+
+ $display("w60_reg = %08x, w61_reg = %08x, w62_reg = %08x, w63_reg = %08x",
+ dut.w_mem[60], dut.w_mem[61], dut.w_mem[62], dut.w_mem[63]);
+
+ $display("w64_reg = %08x, w65_reg = %08x, w66_reg = %08x, w67_reg = %08x",
+ dut.w_mem[64], dut.w_mem[65], dut.w_mem[66], dut.w_mem[67]);
+
+ $display("w68_reg = %08x, w69_reg = %08x, w70_reg = %08x, w71_reg = %08x",
+ dut.w_mem[68], dut.w_mem[69], dut.w_mem[70], dut.w_mem[71]);
+
+ $display("w72_reg = %08x, w73_reg = %08x, w74_reg = %08x, w75_reg = %08x",
+ dut.w_mem[72], dut.w_mem[73], dut.w_mem[74], dut.w_mem[75]);
+
+ $display("w76_reg = %08x, w77_reg = %08x, w78_reg = %08x, w79_reg = %08x",
+ dut.w_mem[76], dut.w_mem[77], dut.w_mem[78], dut.w_mem[79]);
+
+ $display("");
+ end
+ endtask // dump_state
+
+
+ //----------------------------------------------------------------
+ // reset_dut
+ //----------------------------------------------------------------
+ task reset_dut();
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(4 * CLK_HALF_PERIOD);
+ tb_reset_n = 1;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // init_sim
+ //----------------------------------------------------------------
+ task init_sim();
+ begin
+ $display("*** Simulation init.");
+ tb_clk = 0;
+ tb_reset_n = 1;
+ cycle_ctr = 0;
+
+ tb_init = 0;
+ tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ tb_addr = 0;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // dump_mem()
+ //
+ // Dump the contents of the memory by directly reading from
+ // the registers in the dut, not via the read port.
+ //----------------------------------------------------------------
+ task dump_mem();
+ begin
+ $display("*** Dumping memory:");
+ $display("W[00] = 0x%08x", dut.w_mem[00]);
+ $display("W[01] = 0x%08x", dut.w_mem[01]);
+ $display("W[02] = 0x%08x", dut.w_mem[02]);
+ $display("W[03] = 0x%08x", dut.w_mem[03]);
+ $display("W[04] = 0x%08x", dut.w_mem[04]);
+ $display("W[05] = 0x%08x", dut.w_mem[05]);
+ $display("W[06] = 0x%08x", dut.w_mem[06]);
+ $display("W[07] = 0x%08x", dut.w_mem[07]);
+ $display("W[08] = 0x%08x", dut.w_mem[08]);
+ $display("W[09] = 0x%08x", dut.w_mem[09]);
+ $display("W[10] = 0x%08x", dut.w_mem[10]);
+ $display("W[11] = 0x%08x", dut.w_mem[11]);
+ $display("W[12] = 0x%08x", dut.w_mem[12]);
+ $display("W[13] = 0x%08x", dut.w_mem[13]);
+ $display("W[14] = 0x%08x", dut.w_mem[14]);
+ $display("W[15] = 0x%08x", dut.w_mem[15]);
+ $display("");
+ end
+ endtask // dump_mem
+
+
+ //----------------------------------------------------------------
+ // test_w_schedule()
+ //
+ // Test that W scheduling happens and work correctly.
+ // Note: Currently not a self checking test case.
+ //----------------------------------------------------------------
+ task test_w_schedule();
+ begin
+ $display("*** Test of W schedule processing. --");
+ tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
+ tb_init = 1;
+ #(4 * CLK_HALF_PERIOD);
+ tb_init = 0;
+
+ #(200 * CLK_HALF_PERIOD);
+
+ dump_w_state();
+ end
+ endtask // test_w_schedule
+
+
+ //----------------------------------------------------------------
+ // test_read_w/(
+ //
+ // Test that we can read data from all W registers.
+ // Note: Currently not a self checking test case.
+ //----------------------------------------------------------------
+ task test_read_w();
+ reg [7 : 0] i;
+ begin
+ $display("*** Test of W read operations. --");
+ i = 0;
+ while (i < 80)
+ begin
+ tb_addr = i;
+ $display("API: w%02x, internal w%02x = 0x%02x", tb_addr, dut.addr, dut.w_tmp);
+ i = i + 1;
+ #(2 * CLK_HALF_PERIOD);
+ end
+ end
+ endtask // read_w
+
+
+ //----------------------------------------------------------------
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : w_mem_test
+ $display(" -- Testbench for sha1 w memory started --");
+ init_sim();
+
+ dump_mem();
+ reset_dut();
+ dump_mem();
+
+ test_w_schedule();
+
+ test_read_w();
+
+ $display("*** Simulation done.");
+ $finish;
+ end
+
+endmodule // w_mem_test
+
+//======================================================================
+// EOF tb_sha1_w_mem.v
+//======================================================================