diff options
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_sha1.v | 5 | ||||
| -rw-r--r-- | src/tb/tb_sha1_core.v | 38 |
2 files changed, 26 insertions, 17 deletions
diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v index 1bc10e8..c3c8eda 100644 --- a/src/tb/tb_sha1.v +++ b/src/tb/tb_sha1.v @@ -100,6 +100,7 @@ module tb_sha1(); reg [7 : 0] tb_address; reg [31 : 0] tb_data_in; wire [31 : 0] tb_data_out; + wire tb_error; reg [31 : 0] read_data; reg [159 : 0] digest_data; @@ -216,8 +217,8 @@ module tb_sha1(); $display("sha1_ctrl_reg = 0x%01x", dut.core.sha1_ctrl_reg); $display("digest_init = 0x%01x, digest_update = 0x%01x", dut.core.digest_init, dut.core.digest_update); - $display("init_state = 0x%01x, update_state = 0x%01x", - dut.core.init_state, dut.core.update_state); + $display("init_state = 0x%01x, update_state = 0x%01x, set_state = 0x%01x", + dut.core.init_state, dut.core.update_state, dut.core.set_state); $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.core.first_block, dut.core.ready_flag, dut.core.w_init); $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v index ce837a1..c14efa5 100644 --- a/src/tb/tb_sha1_core.v +++ b/src/tb/tb_sha1_core.v @@ -59,7 +59,10 @@ module tb_sha1_core(); reg tb_reset_n; reg tb_init; reg tb_next; + reg tb_set; reg [511 : 0] tb_block; + reg [159 : 0] tb_state_in; + wire [159 : 0] tb_state_out; wire tb_ready; wire [159 : 0] tb_digest; wire tb_digest_valid; @@ -70,19 +73,23 @@ module tb_sha1_core(); // Device Under Test. //---------------------------------------------------------------- sha1_core dut( - .clk(tb_clk), - .reset_n(tb_reset_n), + .clk(tb_clk), + .reset_n(tb_reset_n), - .init(tb_init), - .next(tb_next), + .init(tb_init), + .next(tb_next), + .set(tb_set), - .block(tb_block), + .block(tb_block), - .ready(tb_ready), + .state_in(tb_state_in), + .state_out(tb_state_out), - .digest(tb_digest), - .digest_valid(tb_digest_valid) - ); + .ready(tb_ready), + + .digest(tb_digest), + .digest_valid(tb_digest_valid) + ); //---------------------------------------------------------------- @@ -181,12 +188,13 @@ module tb_sha1_core(); error_ctr = 0; tc_ctr = 0; - tb_clk = 0; - tb_reset_n = 1; - - tb_init = 0; - tb_next = 0; - tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + tb_clk = 0; + tb_reset_n = 1; + tb_init = 0; + tb_next = 0; + tb_set = 0; + tb_state_in = 160'h0; + tb_block = 512'h0; end endtask // init_dut |