index
:
core/comm/uart
master
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
rtl
Mode
Name
Size
-rw-r--r--
uart.v
8501
log
plain
blame
-rw-r--r--
uart_core.v
17055
log
plain
blame
