| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-05-09 | Update of core address size to 8 bits. Changed use of bit rate, data and ↵ | Joachim Strömbergson | |
| stop bits from the top. | |||
| 2014-03-13 | Adding testbench for the uart. | Joachim Strömbergson | |
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index : core/comm/uart | |
| A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
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