| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-09 | Update of core address size to 8 bits. Changed use of bit rate, data and stop... | Joachim StroĢmbergson |
| 2014-03-13 | Adding testbench for the uart. | Joachim StroĢmbergson |
 |
index : core/comm/uart | |
| A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
| aboutsummaryrefslogtreecommitdiff |