diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/uart_core.v | 34 |
1 files changed, 13 insertions, 21 deletions
diff --git a/src/rtl/uart_core.v b/src/rtl/uart_core.v index af2f5a0..14a7ef7 100644 --- a/src/rtl/uart_core.v +++ b/src/rtl/uart_core.v @@ -16,7 +16,7 @@ // // // Author: Joachim Strombergson -// Copyright (c) 2014 SUNET +// Copyright (c) 2014, SUNET // // Redistribution and use in source and binary forms, with or // without modification, are permitted provided that the following @@ -51,6 +51,7 @@ module uart_core( // Configuration parameters input wire [15 : 0] bit_rate, + input wire [3 : 0] data_bits, input wire [1 : 0] stop_bits, // External data interface @@ -72,18 +73,6 @@ module uart_core( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - // The default clock rate is based on target clock frequency - // divided by the bit rate times in order to hit the - // center of the bits. I.e. - // Clock: 50 MHz - // Bitrate: 19200 bps - // Divisor = 50*10E6 / 9600 = 5208 - parameter DEFAULT_CLK_RATE = 5208; - parameter DEFAULT_HALF_CLK_RATE = DEFAULT_CLK_RATE / 2; - - parameter DEFAULT_DATA_BITS = 8; - parameter DEFAULT_STOP_BITS = 1; - parameter ERX_IDLE = 0; parameter ERX_START = 1; parameter ERX_BITS = 2; @@ -157,6 +146,7 @@ module uart_core( //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- + wire [15 : 0] half_bit_rate; //---------------------------------------------------------------- @@ -166,6 +156,8 @@ module uart_core( assign rxd_syn = rxd_syn_reg; assign rxd_data = rxd_byte_reg; assign txd_ack = txd_ack_reg; + + assign half_bit_rate = {1'b0, bit_rate[15 : 1]}; //---------------------------------------------------------------- @@ -402,7 +394,7 @@ module uart_core( end else begin - if (rxd_bitrate_ctr_reg == DEFAULT_HALF_CLK_RATE) + if (rxd_bitrate_ctr_reg == half_bit_rate) begin // start bit assumed. We start sampling data. rxd_bit_ctr_rst = 1; @@ -416,7 +408,7 @@ module uart_core( ERX_BITS: begin - if (rxd_bitrate_ctr_reg < DEFAULT_CLK_RATE) + if (rxd_bitrate_ctr_reg < bit_rate) begin rxd_bitrate_ctr_inc = 1; end @@ -425,7 +417,7 @@ module uart_core( rxd_byte_we = 1; rxd_bit_ctr_inc = 1; rxd_bitrate_ctr_rst = 1; - if (rxd_bit_ctr_reg == DEFAULT_DATA_BITS - 1) + if (rxd_bit_ctr_reg == data_bits - 1) begin erx_ctrl_new = ERX_STOP; erx_ctrl_we = 1; @@ -437,7 +429,7 @@ module uart_core( ERX_STOP: begin rxd_bitrate_ctr_inc = 1; - if (rxd_bitrate_ctr_reg == DEFAULT_CLK_RATE * DEFAULT_STOP_BITS) + if (rxd_bitrate_ctr_reg == bit_rate * stop_bits) begin rxd_syn_new = 1; rxd_syn_we = 1; @@ -521,7 +513,7 @@ module uart_core( ETX_START: begin - if (txd_bitrate_ctr_reg == DEFAULT_CLK_RATE) + if (txd_bitrate_ctr_reg == bit_rate) begin txd_bit_ctr_rst = 1; etx_ctrl_new = ETX_BITS; @@ -536,7 +528,7 @@ module uart_core( ETX_BITS: begin - if (txd_bitrate_ctr_reg < DEFAULT_CLK_RATE) + if (txd_bitrate_ctr_reg < bit_rate) begin txd_bitrate_ctr_inc = 1; end @@ -544,7 +536,7 @@ module uart_core( begin txd_bitrate_ctr_rst = 1; - if (txd_bit_ctr_reg == DEFAULT_DATA_BITS) + if (txd_bit_ctr_reg == data_bits) begin txd_new = 1; txd_we = 1; @@ -564,7 +556,7 @@ module uart_core( ETX_STOP: begin txd_bitrate_ctr_inc = 1; - if (txd_bitrate_ctr_reg == DEFAULT_CLK_RATE * DEFAULT_STOP_BITS) + if (txd_bitrate_ctr_reg == bit_rate * stop_bits) begin etx_ctrl_new = ETX_IDLE; etx_ctrl_we = 1; |