diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/tb/tb_uart.v | 101 |
1 files changed, 59 insertions, 42 deletions
diff --git a/src/tb/tb_uart.v b/src/tb/tb_uart.v index 1abdd34..6bf18bf 100644 --- a/src/tb/tb_uart.v +++ b/src/tb/tb_uart.v @@ -51,7 +51,11 @@ module tb_uart(); parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = CLK_HALF_PERIOD * 2; - + + // from uart_regs.v + parameter DEFAULT_BIT_RATE = 16'd5208; + parameter DEFAULT_DATA_BITS = 4'h8; + parameter DEFAULT_STOP_BITS = 2'h1; //---------------------------------------------------------------- // Register and Wire declarations. @@ -80,36 +84,46 @@ module tb_uart(); reg txd_state; - //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- - uart dut( - .clk(tb_clk), - .reset_n(tb_reset_n), - - .rxd(tb_rxd), - .txd(tb_txd), - - .rxd_syn(tb_rxd_syn), - .rxd_data(tb_rxd_data), - .rxd_ack(tb_rxd_ack), - - // Internal transmit interface. - .txd_syn(tb_txd_syn), - .txd_data(tb_txd_data), - .txd_ack(tb_txd_ack), - - // API interface. - .cs(tb_cs), - .we(tb_we), - .address(tb_address), - .write_data(tb_write_data), - .read_data(tb_read_data), - .error(tb_error), - - .debug(tb_debug) - ); + uart_core dut_core + ( + .clk(tb_clk), + .reset_n(tb_reset_n), + + // Configuration parameters + .bit_rate(DEFAULT_BIT_RATE), + .data_bits(DEFAULT_DATA_BITS), + .stop_bits(DEFAULT_STOP_BITS), + + // External data interface + .rxd(tb_rxd), + .txd(tb_txd), + + // Internal receive interface. + .rxd_syn(tb_rxd_syn), + .rxd_data(tb_rxd_data), + .rxd_ack(tb_rxd_ack), + + // Internal transmit interface. + .txd_syn(tb_txd_syn), + .txd_data(tb_txd_data), + .txd_ack(tb_txd_ack) + ); + +// comm_regs dut_regs( +// .clk(tb_clk), +// .rst(~tb_reset_n), +// +// // API interface. +// .cs(tb_cs), +// .we(tb_we), +// .address(tb_address), +// .write_data(tb_write_data), +// .read_data(tb_read_data), +// .error(tb_error) +// ); //---------------------------------------------------------------- // Concurrent assignments. @@ -183,23 +197,23 @@ module tb_uart(); $display("------------"); $display("Inputs and outputs:"); $display("rxd = 0x%01x, txd = 0x%01x,", - dut.core.rxd, dut.core.txd); + dut_core.rxd, dut_core.txd); $display(""); $display("Sample and data registers:"); $display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x", - dut.core.rxd_reg, dut.core.rxd_byte_reg); + dut_core.rxd_reg, dut_core.rxd_byte_reg); $display(""); $display("Counters:"); $display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x", - dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg); + dut_core.rxd_bit_ctr_reg, dut_core.rxd_bitrate_ctr_reg); $display(""); $display("Control signals and FSM state:"); $display("erx_ctrl_reg = 0x%02x", - dut.core.erx_ctrl_reg); + dut_core.erx_ctrl_reg); $display(""); end endtask // dump_dut_state @@ -214,8 +228,8 @@ module tb_uart(); task dump_rx_state(); begin $display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x", - dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg, - dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg); + dut_core.rxd, dut_core.rxd_reg, dut_core.rxd_byte_reg, dut_core.rxd_bit_ctr_reg, + dut_core.rxd_bitrate_ctr_reg, dut_core.rxd_syn, dut_core.erx_ctrl_reg); end endtask // dump_dut_state @@ -229,8 +243,8 @@ module tb_uart(); task dump_tx_state(); begin $display("txd = 0x%01x, txd_reg = 0x%01x, txd_byte_reg = 0x%01x, txd_bit_ctr_reg = 0x%01x, txd_bitrate_ctr_reg = 0x%02x, txd_ack = 0x%01x, etx_ctrl_reg = 0x%02x", - dut.core.txd, dut.core.txd_reg, dut.core.txd_byte_reg, dut.core.txd_bit_ctr_reg, - dut.core.txd_bitrate_ctr_reg, dut.core.txd_ack, dut.core.etx_ctrl_reg); + dut_core.txd, dut_core.txd_reg, dut_core.txd_byte_reg, dut_core.txd_bit_ctr_reg, + dut_core.txd_bitrate_ctr_reg, dut_core.txd_ack, dut_core.etx_ctrl_reg); end endtask // dump_dut_state @@ -288,20 +302,23 @@ module tb_uart(); // Start bit $display("*** Transmitting start bit."); tb_rxd = 0; - #(CLK_PERIOD * dut.DEFAULT_BIT_RATE); +// #(CLK_PERIOD * dut_regs.DEFAULT_BIT_RATE); + #(CLK_PERIOD * DEFAULT_BIT_RATE); // Send the bits LSB first. for (i = 0 ; i < 8 ; i = i + 1) begin $display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]); tb_rxd = data[i]; - #(CLK_PERIOD * dut.DEFAULT_BIT_RATE); +// #(CLK_PERIOD * dut_regs.DEFAULT_BIT_RATE); + #(CLK_PERIOD * DEFAULT_BIT_RATE); end // Send two stop bits. I.e. two bit times high (mark) value. $display("*** Transmitting two stop bits."); tb_rxd = 1; - #(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS); +// #(2 * CLK_PERIOD * dut_regs.DEFAULT_BIT_RATE * dut_regs.DEFAULT_STOP_BITS); + #(2 * CLK_PERIOD * DEFAULT_BIT_RATE * DEFAULT_STOP_BITS); $display("*** End of transmission."); end endtask // transmit_byte @@ -319,15 +336,15 @@ module tb_uart(); transmit_byte(data); - if (dut.core.rxd_byte_reg == data) + if (dut_core.rxd_byte_reg == data) begin $display("*** Correct data: 0x%01x captured by the dut.", - dut.core.rxd_byte_reg); + dut_core.rxd_byte_reg); end else begin $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.", - dut.core.rxd_byte_reg, data); + dut_core.rxd_byte_reg, data); error_ctr = error_ctr + 1; end end |