| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| master | whack copyrights | Paul Selkirk | 9 years | |
| Age | Commit message | Author | ||
| 2015-12-13 | whack copyrightsHEADmaster | Paul Selkirk | ||
| 2015-03-31 | Fix testbench to match new file organization. | Paul Selkirk | ||
| 2015-03-31 | Don't delay register reads in uart_regs. | Paul Selkirk | ||
| 2015-03-17 | Rearrange cores. | Paul Selkirk | ||
| 2014-11-07 | Changed to asynch reset. | Joachim Strömbergson | ||
| 2014-05-09 | Adding a note about the new ability to change bit rate as well as number of d... | Joachim Strömbergson | ||
| 2014-05-09 | Update of core address size to 8 bits. Changed use of bit rate, data and stop... | Joachim Strömbergson | ||
| 2014-05-09 | Update of core to use bitrate, data bits and stop bits supplied via ports. | Joachim Strömbergson | ||
| 2014-05-09 | Adding support for setting bit rate, data- and stop bits. | Joachim Strömbergson | ||
| 2014-03-17 | Changing from blocking to correct, non-blocking assignments in reg update. | Joachim Strömbergson | ||
| [...] | ||||
| Clone | ||||
| https://git.cryptech.is/core/comm/uart | ||||
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index : core/comm/uart | |
| A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
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